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-rw-r--r--tests/ice40/adffs.ys8
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index f82da6b14..548060b66 100644
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -4,8 +4,8 @@ flatten
equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFFNSR
+select -assert-count 1 t:SB_DFFNS
select -assert-count 2 t:SB_DFFR
-select -assert-count 1 t:SB_DFFSS
-select -assert-count 1 t:SB_LUT4
-select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D
+select -assert-count 1 t:SB_DFFS
+select -assert-count 2 t:SB_LUT4
+select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D