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Diffstat (limited to 'tests/ice40/adffs.ys')
| -rw-r--r-- | tests/ice40/adffs.ys | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index 14b251c5c..f82da6b14 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,12 +1,11 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFF -select -assert-count 1 t:SB_DFFN -select -assert-count 2 t:SB_DFFSR -select -assert-count 7 t:SB_LUT4 -select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D +select -assert-count 1 t:SB_DFFNSR +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFSS +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D |