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-rw-r--r--tests/memories/read_arst.v27
-rw-r--r--tests/memories/read_two_mux.v5
-rwxr-xr-xtests/memories/run-test.sh38
-rw-r--r--tests/memories/trans_addr_enable.v21
-rw-r--r--tests/memories/trans_sdp.v21
-rw-r--r--tests/memories/trans_sp.v21
-rw-r--r--tests/memories/wide_all.v36
-rw-r--r--tests/memories/wide_read_async.v27
-rw-r--r--tests/memories/wide_read_mixed.v46
-rw-r--r--tests/memories/wide_read_sync.v32
-rw-r--r--tests/memories/wide_read_trans.v40
-rw-r--r--tests/memories/wide_thru_priority.v29
-rw-r--r--tests/memories/wide_write.v29
13 files changed, 368 insertions, 4 deletions
diff --git a/tests/memories/read_arst.v b/tests/memories/read_arst.v
new file mode 100644
index 000000000..6100cc4a7
--- /dev/null
+++ b/tests/memories/read_arst.v
@@ -0,0 +1,27 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+// expect-rd-en \re
+// expect-rd-arst-sig \reset
+// expect-rd-arst-val 8'01011010
+// expect-rd-init-val 8'00111100
+
+module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
+
+reg [7:0] bram[0:255];
+initial rdata = 8'h3c;
+
+always @(posedge clk) begin
+ if (we)
+ bram[addr] <= wdata;
+end
+
+always @(posedge clk, posedge reset) begin
+ if (reset)
+ rdata <= 8'h5a;
+ else if (re)
+ rdata <= bram[addr];
+end
+
+endmodule
+
diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v
index 4f2e7e1cd..8b609c552 100644
--- a/tests/memories/read_two_mux.v
+++ b/tests/memories/read_two_mux.v
@@ -1,6 +1,9 @@
// expect-wr-ports 1
// expect-rd-ports 1
-// expect-no-rd-clk
+// expect-rd-clk \clk
+// expect-rd-en \re
+// expect-rd-srst-sig \reset
+// expect-rd-srst-val 8'00000000
module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index 8d1a8b413..c65066a9c 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -9,20 +9,24 @@ while getopts "A:S:" opt
do
case "$opt" in
A) abcopt="-A $OPTARG" ;;
- S) seed="-S $OPTARG" ;;
+ S) seed="$OPTARG" ;;
esac
done
shift "$((OPTIND-1))"
-bash ../tools/autotest.sh $abcopt $seed -G *.v
+${MAKE:-make} -f ../tools/autotest.mk SEED="$seed" EXTRA_FLAGS="$abcopt" *.v
for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
echo -n "Testing expectations for $f .."
- ../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem" $f
+ ../../yosys -f verilog -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f
if grep -q expect-wr-ports $f; then
grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
{ echo " ERROR: Unexpected number of write ports."; false; }
fi
+ if grep -q expect-wr-wide-continuation $f; then
+ grep -q "parameter \\\\WR_WIDE_CONTINUATION $(gawk '/expect-wr-wide-continuation/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+ { echo " ERROR: Unexpected write wide continuation."; false; }
+ fi
if grep -q expect-rd-ports $f; then
grep -q "parameter \\\\RD_PORTS $(gawk '/expect-rd-ports/ { print $3; }' $f)\$" ${f%.v}.dmp ||
{ echo " ERROR: Unexpected number of read ports."; false; }
@@ -31,6 +35,34 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
{ echo " ERROR: Unexpected read clock."; false; }
fi
+ if grep -q expect-rd-en $f; then
+ grep -q "connect \\\\RD_EN \\$(gawk '/expect-rd-en/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+ { echo " ERROR: Unexpected read enable."; false; }
+ fi
+ if grep -q expect-rd-srst-sig $f; then
+ grep -q "connect \\\\RD_SRST \\$(gawk '/expect-rd-srst-sig/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+ { echo " ERROR: Unexpected read sync reset."; false; }
+ fi
+ if grep -q expect-rd-srst-val $f; then
+ grep -q "parameter \\\\RD_SRST_VALUE $(gawk '/expect-rd-srst-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+ { echo " ERROR: Unexpected read sync reset value."; false; }
+ fi
+ if grep -q expect-rd-arst-sig $f; then
+ grep -q "connect \\\\RD_ARST \\$(gawk '/expect-rd-arst-sig/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+ { echo " ERROR: Unexpected read async reset."; false; }
+ fi
+ if grep -q expect-rd-arst-val $f; then
+ grep -q "parameter \\\\RD_ARST_VALUE $(gawk '/expect-rd-arst-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+ { echo " ERROR: Unexpected read async reset value."; false; }
+ fi
+ if grep -q expect-rd-init-val $f; then
+ grep -q "parameter \\\\RD_INIT_VALUE $(gawk '/expect-rd-init-val/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+ { echo " ERROR: Unexpected read init value."; false; }
+ fi
+ if grep -q expect-rd-wide-continuation $f; then
+ grep -q "parameter \\\\RD_WIDE_CONTINUATION $(gawk '/expect-rd-wide-continuation/ { print $3; }' $f)\$" ${f%.v}.dmp ||
+ { echo " ERROR: Unexpected read wide continuation."; false; }
+ fi
if grep -q expect-no-rd-clk $f; then
grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
{ echo " ERROR: Expected no read clock."; false; }
diff --git a/tests/memories/trans_addr_enable.v b/tests/memories/trans_addr_enable.v
new file mode 100644
index 000000000..f366f41ad
--- /dev/null
+++ b/tests/memories/trans_addr_enable.v
@@ -0,0 +1,21 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+
+module top(input clk, we, rae, input [7:0] addr, wd, output [7:0] rd);
+
+reg [7:0] mem[0:255];
+
+reg [7:0] rra;
+
+always @(posedge clk) begin
+ if (we)
+ mem[addr] <= wd;
+
+ if (rae)
+ rra <= addr;
+end
+
+assign rd = mem[rra];
+
+endmodule
diff --git a/tests/memories/trans_sdp.v b/tests/memories/trans_sdp.v
new file mode 100644
index 000000000..b89f2ccf0
--- /dev/null
+++ b/tests/memories/trans_sdp.v
@@ -0,0 +1,21 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+// expect-rd-en \re
+
+module top(input clk, we, re, input [7:0] ra, wa, wd, output reg [7:0] rd);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+ if (we)
+ mem[wa] <= wd;
+
+ if (re) begin
+ rd <= mem[ra];
+ if (we && ra == wa)
+ rd <= wd;
+ end
+end
+
+endmodule
diff --git a/tests/memories/trans_sp.v b/tests/memories/trans_sp.v
new file mode 100644
index 000000000..ddd41a13e
--- /dev/null
+++ b/tests/memories/trans_sp.v
@@ -0,0 +1,21 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+// expect-rd-en \re
+
+module top(input clk, we, re, input [7:0] addr, wd, output reg [7:0] rd);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+ if (we)
+ mem[addr] <= wd;
+
+ if (re) begin
+ rd <= mem[addr];
+ if (we)
+ rd <= wd;
+ end
+end
+
+endmodule
diff --git a/tests/memories/wide_all.v b/tests/memories/wide_all.v
new file mode 100644
index 000000000..f7bc3e5ce
--- /dev/null
+++ b/tests/memories/wide_all.v
@@ -0,0 +1,36 @@
+// expect-wr-ports 2
+// expect-rd-ports 1
+// expect-wr-wide-continuation 2'10
+
+module test(
+ input clk,
+ input [3:0] we,
+ input [6:0] ra,
+ input [5:0] wa,
+ input [31:0] wd,
+ output [15:0] rd
+);
+
+reg [7:0] mem[3:254];
+
+assign rd[7:0] = mem[{ra, 1'b0}];
+assign rd[15:0] = mem[{ra, 1'b1}];
+
+initial begin
+ mem[5] = 8'h12;
+ mem[6] = 8'h34;
+ mem[7] = 8'h56;
+end
+
+always @(posedge clk) begin
+ if (we[0])
+ mem[{wa, 2'b00}] <= wd[7:0];
+ if (we[1])
+ mem[{wa, 2'b01}] <= wd[15:8];
+ if (we[2])
+ mem[{wa, 2'b10}] <= wd[23:16];
+ if (we[3])
+ mem[{wa, 2'b11}] <= wd[31:24];
+end
+
+endmodule
diff --git a/tests/memories/wide_read_async.v b/tests/memories/wide_read_async.v
new file mode 100644
index 000000000..aecdb1938
--- /dev/null
+++ b/tests/memories/wide_read_async.v
@@ -0,0 +1,27 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+
+module test(
+ input clk,
+ input we,
+ input [5:0] ra,
+ input [7:0] wa,
+ input [7:0] wd,
+ output [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+assign rd[7:0] = mem[{ra, 2'b00}];
+assign rd[15:8] = mem[{ra, 2'b01}];
+assign rd[23:16] = mem[{ra, 2'b10}];
+assign rd[31:24] = mem[{ra, 2'b11}];
+
+always @(posedge clk) begin
+ if (we)
+ mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_read_mixed.v b/tests/memories/wide_read_mixed.v
new file mode 100644
index 000000000..c36db3d31
--- /dev/null
+++ b/tests/memories/wide_read_mixed.v
@@ -0,0 +1,46 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+// expect-rd-srst-val 32'10000111011001010100001100100001
+// expect-rd-init-val 32'10101011110011011110111110101011
+
+// In this testcase, the byte-wide read ports are merged into a single
+// word-wide port despite mismatched transparency, with soft transparency
+// logic inserted on half the port to preserve the semantics.
+
+module test(
+ input clk,
+ input re, rr,
+ input we,
+ input [5:0] ra,
+ input [7:0] wa,
+ input [7:0] wd,
+ output reg [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+initial rd = 32'habcdefab;
+
+always @(posedge clk) begin
+ if (rr) begin
+ rd <= 32'h87654321;
+ end else if (re) begin
+ rd[7:0] <= mem[{ra, 2'b00}];
+ rd[15:8] <= mem[{ra, 2'b01}];
+ rd[23:16] <= mem[{ra, 2'b10}];
+ rd[31:24] <= mem[{ra, 2'b11}];
+ if (we && wa == {ra, 2'b00})
+ rd [7:0] <= wd;
+ if (we && wa == {ra, 2'b01})
+ rd [15:8] <= wd;
+ end
+end
+
+always @(posedge clk) begin
+ if (we)
+ mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_read_sync.v b/tests/memories/wide_read_sync.v
new file mode 100644
index 000000000..54ba3f256
--- /dev/null
+++ b/tests/memories/wide_read_sync.v
@@ -0,0 +1,32 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+
+module test(
+ input clk,
+ input re,
+ input we,
+ input [5:0] ra,
+ input [7:0] wa,
+ input [7:0] wd,
+ output reg [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+ if (re) begin
+ rd[7:0] <= mem[{ra, 2'b00}];
+ rd[15:8] <= mem[{ra, 2'b01}];
+ rd[23:16] <= mem[{ra, 2'b10}];
+ rd[31:24] <= mem[{ra, 2'b11}];
+ end
+end
+
+always @(posedge clk) begin
+ if (we)
+ mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_read_trans.v b/tests/memories/wide_read_trans.v
new file mode 100644
index 000000000..fe3293500
--- /dev/null
+++ b/tests/memories/wide_read_trans.v
@@ -0,0 +1,40 @@
+// expect-wr-ports 1
+// expect-rd-ports 4
+// expect-rd-wide-continuation 4'1110
+
+module test(
+ input clk,
+ input re,
+ input we,
+ input [5:0] ra,
+ input [7:0] wa,
+ input [7:0] wd,
+ output reg [31:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+always @(posedge clk) begin
+ if (re) begin
+ rd[7:0] <= mem[{ra, 2'b00}];
+ rd[15:8] <= mem[{ra, 2'b01}];
+ rd[23:16] <= mem[{ra, 2'b10}];
+ rd[31:24] <= mem[{ra, 2'b11}];
+ if (we && wa == {ra, 2'b00})
+ rd [7:0] <= wd;
+ if (we && wa == {ra, 2'b01})
+ rd [15:8] <= wd;
+ if (we && wa == {ra, 2'b10})
+ rd [23:16] <= wd;
+ if (we && wa == {ra, 2'b11})
+ rd [31:24] <= wd;
+ end
+end
+
+always @(posedge clk) begin
+ if (we)
+ mem[wa] <= wd;
+end
+
+endmodule
+
diff --git a/tests/memories/wide_thru_priority.v b/tests/memories/wide_thru_priority.v
new file mode 100644
index 000000000..10c0d837b
--- /dev/null
+++ b/tests/memories/wide_thru_priority.v
@@ -0,0 +1,29 @@
+// expect-wr-ports 3
+// expect-rd-ports 1
+// expect-wr-wide-continuation 3'010
+
+module test(
+ input clk,
+ input we1, we2,
+ input [5:0] ra,
+ input [4:0] wa1,
+ input [5:0] wa2,
+ input [15:0] wd1,
+ input [7:0] wd2,
+ output [7:0] rd
+);
+
+reg [7:0] mem[0:63];
+
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+ if (we1)
+ mem[{wa1, 1'b0}] <= wd1[7:0];
+ if (we2)
+ mem[wa2] <= wd2;
+ if (we1)
+ mem[{wa1, 1'b1}] <= wd1[15:8];
+end
+
+endmodule
diff --git a/tests/memories/wide_write.v b/tests/memories/wide_write.v
new file mode 100644
index 000000000..5c4cc41f9
--- /dev/null
+++ b/tests/memories/wide_write.v
@@ -0,0 +1,29 @@
+// expect-wr-ports 4
+// expect-rd-ports 1
+// expect-wr-wide-continuation 4'1110
+
+module test(
+ input clk,
+ input [3:0] we,
+ input [7:0] ra,
+ input [5:0] wa,
+ input [31:0] wd,
+ output [7:0] rd
+);
+
+reg [7:0] mem[0:255];
+
+assign rd = mem[ra];
+
+always @(posedge clk) begin
+ if (we[0])
+ mem[{wa, 2'b00}] <= wd[7:0];
+ if (we[1])
+ mem[{wa, 2'b01}] <= wd[15:8];
+ if (we[2])
+ mem[{wa, 2'b10}] <= wd[23:16];
+ if (we[3])
+ mem[{wa, 2'b11}] <= wd[31:24];
+end
+
+endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 18:51:43 +0000