diff options
Diffstat (limited to 'tests/opt/opt_expr.ys')
| -rw-r--r-- | tests/opt/opt_expr.ys | 95 |
1 files changed, 23 insertions, 72 deletions
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 0c61ac881..9f3c0a1cd 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -6,24 +6,16 @@ endmodule EOT hierarchy -auto-top -proc -design -save gold -opt_expr -fine -wreduce +equiv_opt -assert opt_expr -fine +design -load postopt +wreduce select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - ########## +design -reset read_verilog <<EOT module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); assign o = (i << 4) + j; @@ -31,24 +23,16 @@ endmodule EOT hierarchy -auto-top -proc -design -save gold -opt_expr -fine -wreduce +equiv_opt -assert opt_expr -fine +design -load postopt +wreduce select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - ########## +design -reset read_verilog <<EOT module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); assign o = j - (i << 4); @@ -56,24 +40,16 @@ endmodule EOT hierarchy -auto-top -proc -design -save gold -opt_expr -fine -wreduce +equiv_opt -assert opt_expr -fine +design -load postopt +wreduce select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - ########## +design -reset read_verilog <<EOT module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); assign o = j - (i << 4); @@ -81,24 +57,16 @@ endmodule EOT hierarchy -auto-top -proc -design -save gold -opt_expr -fine -wreduce +equiv_opt -assert opt_expr -fine +design -load postopt +wreduce select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - ########## +design -reset read_verilog <<EOT module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); assign o = (i << 4) - j; @@ -106,24 +74,16 @@ endmodule EOT hierarchy -auto-top -proc -design -save gold -opt_expr -fine -wreduce +equiv_opt -assert opt_expr -fine +design -load postopt +wreduce select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - ########## +design -reset read_verilog <<EOT module opt_expr_sub_test4(input [3:0] i, output [8:0] o); assign o = 5'b00010 - i; @@ -131,18 +91,9 @@ endmodule EOT hierarchy -auto-top -proc -design -save gold -opt_expr -fine -wreduce +equiv_opt -assert opt_expr -fine +design -load postopt +wreduce select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter |