diff options
Diffstat (limited to 'tests/opt/opt_expr_alu.ys')
| -rw-r--r-- | tests/opt/opt_expr_alu.ys | 124 |
1 files changed, 115 insertions, 9 deletions
diff --git a/tests/opt/opt_expr_alu.ys b/tests/opt/opt_expr_alu.ys index a3361ca43..9121c0096 100644 --- a/tests/opt/opt_expr_alu.ys +++ b/tests/opt/opt_expr_alu.ys @@ -5,10 +5,10 @@ endmodule EOT alumacc -equiv_opt opt_expr -fine +equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$pos -select -assert-count none t:$pos t:* %D +select -assert-none t:$pos t:* %D design -reset @@ -20,7 +20,7 @@ EOT alumacc select -assert-count 1 t:$alu -select -assert-count none t:$alu t:* %D +select -assert-none t:$alu t:* %D design -reset @@ -30,10 +30,10 @@ assign y = {a,1'b1} - 1'b1; endmodule EOT -equiv_opt opt_expr -fine +equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$pos -select -assert-count none t:$pos t:* %D +select -assert-none t:$pos t:* %D design -reset @@ -43,10 +43,10 @@ assign y = {a,3'b101} - 1'b1; endmodule EOT -equiv_opt opt_expr -fine +equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$pos -select -assert-count none t:$pos t:* %D +select -assert-none t:$pos t:* %D design -reset @@ -57,7 +57,113 @@ endmodule EOT alumacc -equiv_opt opt_expr -fine +equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$pos -select -assert-count none t:$pos t:* %D +select -assert-count 1 t:$not +select -assert-none t:$pos t:$not %% t:* %D + + +design -reset +read_verilog <<EOT +module test(input [1:0] a, output [3:0] y); +assign y = -{a[1], 2'b10, a[0]}; +endmodule +EOT + +alumacc +equiv_opt -assert opt -fine +design -load postopt +select -assert-count 1 t:$alu +select -assert-count 1 t:$alu r:Y_WIDTH=3 %i +select -assert-count 1 t:$not +select -assert-none t:$alu t:$not t:* %D %D + + +design -reset +read_verilog <<EOT +module test(input [3:0] a, input [2:0] b, output [5:0] y); +assign y = {a[3:2], 1'b1, a[1:0]} + {b[2], 2'b11, b[1:0]}; +endmodule +EOT + +alumacc +equiv_opt -assert opt -fine +design -load postopt +dump +select -assert-count 2 t:$alu +select -assert-count 1 t:$alu r:Y_WIDTH=2 %i +select -assert-count 1 t:$alu r:Y_WIDTH=3 %i +select -assert-none t:$alu t:* %D + + +design -reset +read_verilog <<EOT +module test(input [3:0] a, input [3:0] b, output [5:0] y); +assign y = {a[3:2], 1'b0, a[1:0]} + {b[3:2], 1'b0, b[1:0]}; +endmodule +EOT + +alumacc +equiv_opt -assert opt -fine +design -load postopt +select -assert-count 2 t:$alu +select -assert-count 2 t:$alu r:Y_WIDTH=3 %i +select -assert-none t:$alu t:* %D + + +design -reset +read_verilog -icells <<EOT +module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co); +$alu #( + .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4), + .A_SIGNED(0), .B_SIGNED(0), +) alu ( + .A(a), .B(4'h0), + .BI(1'b0), .CI(1'b0), + .Y(y), .X(x), .CO(co), +); +endmodule +EOT + +equiv_opt -assert opt +design -load postopt +select -assert-none t:$alu + + +design -reset +read_verilog -icells <<EOT +module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co); +$alu #( + .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4), + .A_SIGNED(0), .B_SIGNED(0), +) alu ( + .A(a), .B(4'h0), + .BI(1'b1), .CI(1'b1), + .Y(y), .X(x), .CO(co), +); +endmodule +EOT + +equiv_opt -assert opt +design -load postopt +select -assert-none t:$alu + + +design -reset +read_verilog -icells <<EOT +module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co); +$alu #( + .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4), + .A_SIGNED(0), .B_SIGNED(0), +) alu ( + .A(4'h0), .B(a), + .BI(1'b0), .CI(1'b0), + .Y(y), .X(x), .CO(co), +); +endmodule +EOT + +equiv_opt -assert opt +design -load postopt +select -assert-none t:$alu |