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-rw-r--r--tests/opt/opt_lut_ins.ys23
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diff --git a/tests/opt/opt_lut_ins.ys b/tests/opt/opt_lut_ins.ys
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+read_ilang << EOF
+
+module \top
+
+ wire width 4 input 1 \A
+
+ wire output 2 \Y
+
+ cell $lut \lut
+ parameter \LUT 16'1111110011000000
+ parameter \WIDTH 4
+ connect \A \A
+ connect \Y \Y
+ end
+end
+
+EOF
+
+equiv_opt -assert opt_lut_ins
+
+design -load postopt
+
+select -assert-count 1 t:$lut r:WIDTH=3 %i