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-rw-r--r--tests/opt/opt_expr_cmp.v40
-rw-r--r--tests/opt/opt_expr_cmp.ys4
-rw-r--r--tests/opt/opt_lut_elim.il19
-rw-r--r--tests/opt/opt_lut_elim.ys3
-rw-r--r--tests/opt/opt_lut_port.ys1
5 files changed, 67 insertions, 0 deletions
diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v
new file mode 100644
index 000000000..5aff4b80f
--- /dev/null
+++ b/tests/opt/opt_expr_cmp.v
@@ -0,0 +1,40 @@
+module top(...);
+ input [3:0] a;
+
+ output o1_1 = 4'b0000 > a;
+ output o1_2 = 4'b0000 <= a;
+ output o1_3 = 4'b1111 < a;
+ output o1_4 = 4'b1111 >= a;
+ output o1_5 = a < 4'b0000;
+ output o1_6 = a >= 4'b0000;
+ output o1_7 = a > 4'b1111;
+ output o1_8 = a <= 4'b1111;
+
+ output o2_1 = 4'sb0000 > $signed(a);
+ output o2_2 = 4'sb0000 <= $signed(a);
+ output o2_3 = $signed(a) < 4'sb0000;
+ output o2_4 = $signed(a) >= 4'sb0000;
+
+ output o3_1 = 4'b0100 > a;
+ output o3_2 = 4'b0100 <= a;
+ output o3_3 = a < 4'b0100;
+ output o3_4 = a >= 4'b0100;
+
+ output o4_1 = 5'b10000 > a;
+ output o4_2 = 5'b10000 >= a;
+ output o4_3 = 5'b10000 < a;
+ output o4_4 = 5'b10000 <= a;
+ output o4_5 = a < 5'b10000;
+ output o4_6 = a <= 5'b10000;
+ output o4_7 = a > 5'b10000;
+ output o4_8 = a >= 5'b10000;
+
+ output o5_1 = 5'b10100 > a;
+ output o5_2 = 5'b10100 >= a;
+ output o5_3 = 5'b10100 < a;
+ output o5_4 = 5'b10100 <= a;
+ output o5_5 = a < 5'b10100;
+ output o5_6 = a <= 5'b10100;
+ output o5_7 = a > 5'b10100;
+ output o5_8 = a >= 5'b10100;
+endmodule
diff --git a/tests/opt/opt_expr_cmp.ys b/tests/opt/opt_expr_cmp.ys
new file mode 100644
index 000000000..214ce8b11
--- /dev/null
+++ b/tests/opt/opt_expr_cmp.ys
@@ -0,0 +1,4 @@
+read_verilog opt_expr_cmp.v
+equiv_opt -assert opt_expr -fine
+design -load postopt
+select -assert-count 0 t:$gt t:$ge t:$lt t:$le
diff --git a/tests/opt/opt_lut_elim.il b/tests/opt/opt_lut_elim.il
new file mode 100644
index 000000000..75675d983
--- /dev/null
+++ b/tests/opt/opt_lut_elim.il
@@ -0,0 +1,19 @@
+module \test
+ wire input 1 \i
+
+ wire output 2 \o1
+ cell $lut $1
+ parameter \LUT 16'0110100110010110
+ parameter \WIDTH 4
+ connect \A { \i 3'000 }
+ connect \Y \o1
+ end
+
+ wire output 2 \o2
+ cell $lut $2
+ parameter \LUT 16'0110100010010110
+ parameter \WIDTH 4
+ connect \A { \i 3'000 }
+ connect \Y \o2
+ end
+end
diff --git a/tests/opt/opt_lut_elim.ys b/tests/opt/opt_lut_elim.ys
new file mode 100644
index 000000000..8e5e23aea
--- /dev/null
+++ b/tests/opt/opt_lut_elim.ys
@@ -0,0 +1,3 @@
+read_ilang opt_lut_elim.il
+opt_lut
+select -assert-count 0 t:$lut
diff --git a/tests/opt/opt_lut_port.ys b/tests/opt/opt_lut_port.ys
index 51dfd988b..3cb4ecb23 100644
--- a/tests/opt/opt_lut_port.ys
+++ b/tests/opt/opt_lut_port.ys
@@ -1,2 +1,3 @@
read_ilang opt_lut_port.il
+opt_lut
select -assert-count 2 t:$lut