2 files changed, 72 insertions, 0 deletions
diff --git a/tests/opt/opt_lut_ins.ys b/tests/opt/opt_lut_ins.ys
new file mode 100644
index 000000000..82460b164
--- /dev/null
+++ b/tests/opt/opt_lut_ins.ys
@@ -0,0 +1,23 @@
+read_ilang << EOF
+
+module \top
+
+  wire width 4 input 1 \A
+
+  wire output 2 \Y
+
+  cell $lut \lut
+    parameter \LUT 16'1111110011000000
+    parameter \WIDTH 4
+    connect \A \A
+    connect \Y \Y
+  end
+end
+
+EOF
+
+equiv_opt -assert opt_lut_ins
+
+design -load postopt
+
+select -assert-count 1 t:$lut r:WIDTH=3 %i
diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys
new file mode 100644
index 000000000..a29c29df6
--- /dev/null
+++ b/tests/opt/opt_merge_init.ys
@@ -0,0 +1,49 @@
+read_verilog -icells <<EOT
+module top(input clk, i, (* init = 1'b0 *) output o, p);
+  \$dff  #(
+    .CLK_POLARITY(1'h1),
+    .WIDTH(32'd1)
+  ) ffo  (
+    .CLK(clk),
+    .D(i),
+    .Q(o)
+  );
+  \$dff  #(
+    .CLK_POLARITY(1'h1),
+    .WIDTH(32'd1)
+  ) ffp  (
+    .CLK(clk),
+    .D(i),
+    .Q(p)
+  );
+endmodule
+EOT
+
+opt_merge
+select -assert-count 1 a:init=1'0
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input clk, i, (* init = 2'b11 *) output [1:0] o);
+  \$dff  #(
+    .CLK_POLARITY(1'h1),
+    .WIDTH(32'd1)
+  ) ff1  (
+    .CLK(clk),
+    .D(i),
+    .Q(o[1])
+  );
+  \$dff  #(
+    .CLK_POLARITY(1'h1),
+    .WIDTH(32'd1)
+  ) ff0  (
+    .CLK(clk),
+    .D(i),
+    .Q(o[0])
+  );
+endmodule
+EOT
+
+opt_merge
+select -assert-count 1 a:init=2'bx1