1 files changed, 14 insertions, 0 deletions
diff --git a/tests/sat/asserts.v b/tests/sat/asserts.v
new file mode 100644
index 000000000..c6f8095e1
--- /dev/null
+++ b/tests/sat/asserts.v
@@ -0,0 +1,14 @@
+// http://www.reddit.com/r/yosys/comments/1vljks/new_support_for_systemveriloglike_asserts/
+module test(input clk, input rst, output y);
+reg [2:0] state;
+always @(posedge clk) begin
+    if (rst || state == 3) begin
+        state <= 0;
+    end else begin
+        assert(state < 3);
+        state <= state + 1;
+    end
+end
+assign y = state[2];
+assert property (y !== 1'b1);
+endmodule