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-rw-r--r--tests/sim/adffe.v8
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diff --git a/tests/sim/adffe.v b/tests/sim/adffe.v
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+module adffe( input d, clk, rst, en, output reg q );
+ always @( posedge clk, posedge rst )
+ if (rst)
+ q <= 0;
+ else
+ if (en)
+ q <= d;
+endmodule