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-rw-r--r--tests/sim/sim_aldffe.ys6
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/sim/sim_aldffe.ys b/tests/sim/sim_aldffe.ys
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+read_verilog aldffe.v
+proc
+opt_dff
+stat
+select -assert-count 1 t:$aldffe
+sim -clock clk -r tb_aldffe.fst -scope tb_aldffe.uut -sim-cmp aldffe