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-rw-r--r--tests/sim/sim_dlatchsr.ys10
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/sim/sim_dlatchsr.ys b/tests/sim/sim_dlatchsr.ys
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+++ b/tests/sim/sim_dlatchsr.ys
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+read_verilog -icells <<EOT
+module dlatchsr(input d, set, clr, en, output reg q);
+$dlatchsr #(.EN_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b1), .WIDTH(1)) uut (.EN(en), .SET(set), .CLR(clr), .D(d), .Q(q));
+endmodule
+EOT
+proc
+opt_dff
+stat
+select -assert-count 1 t:$dlatchsr
+sim -r tb_dlatchsr.fst -scope tb_dlatchsr.uut -sim-cmp dlatchsr