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-rw-r--r--tests/simple/const_branch_finish.v3
-rw-r--r--tests/simple/const_fold_func.v61
-rw-r--r--tests/simple/const_func_shadow.v33
-rw-r--r--tests/simple/func_block.v33
-rw-r--r--tests/simple/func_recurse.v25
-rw-r--r--tests/simple/func_width_scope.v41
-rw-r--r--tests/simple/genblk_collide.v27
-rw-r--r--tests/simple/genblk_dive.v21
-rw-r--r--tests/simple/genblk_order.v18
-rw-r--r--tests/simple/genblk_port_shadow.v10
-rw-r--r--tests/simple/generate.v71
-rw-r--r--tests/simple/local_loop_var.sv11
-rw-r--r--tests/simple/loop_var_shadow.v15
-rw-r--r--tests/simple/macro_arg_spaces.sv28
-rw-r--r--tests/simple/macro_arg_surrounding_spaces.v20
-rw-r--r--tests/simple/named_genblk.v27
-rw-r--r--tests/simple/nested_genblk_resolve.v14
-rw-r--r--tests/simple/unnamed_block_decl.sv17
18 files changed, 468 insertions, 7 deletions
diff --git a/tests/simple/const_branch_finish.v b/tests/simple/const_branch_finish.v
index 8166688e6..f585be87a 100644
--- a/tests/simple/const_branch_finish.v
+++ b/tests/simple/const_branch_finish.v
@@ -21,9 +21,6 @@ module top;
end
end
generate
- begin : unconditional_block
- initial `CONSTANT_CHECK
- end
if (WIDTH == 32) begin : conditional_block
initial `CONSTANT_CHECK
end
diff --git a/tests/simple/const_fold_func.v b/tests/simple/const_fold_func.v
new file mode 100644
index 000000000..ee2f12e06
--- /dev/null
+++ b/tests/simple/const_fold_func.v
@@ -0,0 +1,61 @@
+module top(
+ input wire [3:0] inp,
+ output wire [3:0] out1, out2, out3, out4, out5,
+ output reg [3:0] out6
+);
+ function automatic [3:0] flip;
+ input [3:0] inp;
+ flip = ~inp;
+ endfunction
+
+ function automatic [3:0] help;
+ input [3:0] inp;
+ help = flip(inp);
+ endfunction
+
+ // while loops are const-eval-only
+ function automatic [3:0] loop;
+ input [3:0] inp;
+ reg [3:0] val;
+ begin
+ val = inp;
+ loop = 1;
+ while (val != inp) begin
+ loop = loop * 2;
+ val = val + 1;
+ end
+ end
+ endfunction
+
+ // not const-eval-only, despite calling a const-eval-only function
+ function automatic [3:0] help_mul;
+ input [3:0] inp;
+ help_mul = inp * loop(2);
+ endfunction
+
+ // can be elaborated so long as exp is a constant
+ function automatic [3:0] pow_flip_a;
+ input [3:0] base, exp;
+ begin
+ pow_flip_a = 1;
+ if (exp > 0)
+ pow_flip_a = base * pow_flip_a(flip(base), exp - 1);
+ end
+ endfunction
+
+ function automatic [3:0] pow_flip_b;
+ input [3:0] base, exp;
+ begin
+ out6[exp] = base & 1;
+ pow_flip_b = 1;
+ if (exp > 0)
+ pow_flip_b = base * pow_flip_b(flip(base), exp - 1);
+ end
+ endfunction
+
+ assign out1 = flip(flip(inp));
+ assign out2 = help(flip(inp));
+ assign out3 = help_mul(inp);
+ assign out4 = pow_flip_a(flip(inp), 3);
+ assign out5 = pow_flip_b(2, 2);
+endmodule
diff --git a/tests/simple/const_func_shadow.v b/tests/simple/const_func_shadow.v
new file mode 100644
index 000000000..ca63606d9
--- /dev/null
+++ b/tests/simple/const_func_shadow.v
@@ -0,0 +1,33 @@
+module top(w, x, y, z);
+ function [11:0] func;
+ input reg [2:0] x;
+ input reg [2:0] y;
+ begin
+ x = x * (y + 1);
+ begin : foo
+ reg [2:0] y;
+ y = x + 1;
+ begin : bar
+ reg [2:0] x;
+ x = y + 1;
+ begin : blah
+ reg [2:0] y;
+ y = x + 1;
+ func[2:0] = y;
+ end
+ func[5:3] = x;
+ end
+ func[8:6] = y;
+ end
+ func[11:9] = x;
+ end
+ endfunction
+ output wire [func(2, 3) - 1:0] w;
+ output wire [func(1, 3) - 1:0] x;
+ output wire [func(3, 1) - 1:0] y;
+ output wire [func(5, 2) - 1:0] z;
+ assign w = 1'sb1;
+ assign x = 1'sb1;
+ assign y = 1'sb1;
+ assign z = 1'sb1;
+endmodule
diff --git a/tests/simple/func_block.v b/tests/simple/func_block.v
new file mode 100644
index 000000000..be759d1a9
--- /dev/null
+++ b/tests/simple/func_block.v
@@ -0,0 +1,33 @@
+`default_nettype none
+
+module top(inp, out1, out2, out3);
+ input wire [31:0] inp;
+
+ function automatic [31:0] func1;
+ input [31:0] inp;
+ reg [31:0] idx;
+ for (idx = 0; idx < 32; idx = idx + 1) begin : blk
+ func1[idx] = (idx & 1'b1) ^ inp[idx];
+ end
+ endfunction
+
+ function automatic [31:0] func2;
+ input [31:0] inp;
+ reg [31:0] idx;
+ for (idx = 0; idx < 32; idx = idx + 1) begin : blk
+ func2[idx] = (idx & 1'b1) ^ inp[idx];
+ end
+ endfunction
+
+ function automatic [31:0] func3;
+ localparam A = 32 - 1;
+ parameter B = 1 - 0;
+ input [31:0] inp;
+ func3[A:B] = inp[A:B];
+ endfunction
+
+ output wire [31:0] out1, out2, out3;
+ assign out1 = func1(inp);
+ assign out2 = func2(inp);
+ assign out3 = func3(inp);
+endmodule
diff --git a/tests/simple/func_recurse.v b/tests/simple/func_recurse.v
new file mode 100644
index 000000000..d61c8cc06
--- /dev/null
+++ b/tests/simple/func_recurse.v
@@ -0,0 +1,25 @@
+module top(
+ input wire [3:0] inp,
+ output wire [3:0] out1, out2
+);
+ function automatic [3:0] pow_a;
+ input [3:0] base, exp;
+ begin
+ pow_a = 1;
+ if (exp > 0)
+ pow_a = base * pow_a(base, exp - 1);
+ end
+ endfunction
+
+ function automatic [3:0] pow_b;
+ input [3:0] base, exp;
+ begin
+ pow_b = 1;
+ if (exp > 0)
+ pow_b = base * pow_b(base, exp - 1);
+ end
+ endfunction
+
+ assign out1 = pow_a(inp, 3);
+ assign out2 = pow_b(2, 2);
+endmodule
diff --git a/tests/simple/func_width_scope.v b/tests/simple/func_width_scope.v
new file mode 100644
index 000000000..ce81e894e
--- /dev/null
+++ b/tests/simple/func_width_scope.v
@@ -0,0 +1,41 @@
+module top(inp, out1, out2);
+ input wire signed inp;
+
+ localparam WIDTH_A = 5;
+ function automatic [WIDTH_A-1:0] func1;
+ input reg [WIDTH_A-1:0] inp;
+ func1 = ~inp;
+ endfunction
+ wire [func1(0)-1:0] xc;
+ assign xc = 1'sb1;
+ wire [WIDTH_A-1:0] xn;
+ assign xn = func1(inp);
+
+ generate
+ if (1) begin : blk
+ localparam WIDTH_A = 6;
+ function automatic [WIDTH_A-1:0] func2;
+ input reg [WIDTH_A-1:0] inp;
+ func2 = ~inp;
+ endfunction
+ wire [func2(0)-1:0] yc;
+ assign yc = 1'sb1;
+ wire [WIDTH_A-1:0] yn;
+ assign yn = func2(inp);
+
+ localparam WIDTH_B = 7;
+ function automatic [WIDTH_B-1:0] func3;
+ input reg [WIDTH_B-1:0] inp;
+ func3 = ~inp;
+ endfunction
+ wire [func3(0)-1:0] zc;
+ assign zc = 1'sb1;
+ wire [WIDTH_B-1:0] zn;
+ assign zn = func3(inp);
+ end
+ endgenerate
+
+ output wire [1023:0] out1, out2;
+ assign out1 = {xc, 1'b0, blk.yc, 1'b0, blk.zc};
+ assign out2 = {xn, 1'b0, blk.yn, 1'b0, blk.zn};
+endmodule
diff --git a/tests/simple/genblk_collide.v b/tests/simple/genblk_collide.v
new file mode 100644
index 000000000..f42dd2cfc
--- /dev/null
+++ b/tests/simple/genblk_collide.v
@@ -0,0 +1,27 @@
+`default_nettype none
+
+module top1;
+ generate
+ if (1) begin : foo
+ if (1) begin : bar
+ wire x;
+ end
+ assign bar.x = 1;
+ wire y;
+ end
+ endgenerate
+endmodule
+
+module top2;
+ genvar i;
+ generate
+ if (1) begin : foo
+ wire x;
+ for (i = 0; i < 1; i = i + 1) begin : foo
+ if (1) begin : foo
+ assign x = 1;
+ end
+ end
+ end
+ endgenerate
+endmodule
diff --git a/tests/simple/genblk_dive.v b/tests/simple/genblk_dive.v
new file mode 100644
index 000000000..98d0e1f4b
--- /dev/null
+++ b/tests/simple/genblk_dive.v
@@ -0,0 +1,21 @@
+`default_nettype none
+module top(output wire x);
+ generate
+ if (1) begin : Z
+ if (1) begin : A
+ wire x;
+ if (1) begin : B
+ wire x;
+ if (1) begin : C
+ wire x;
+ assign B.x = 0;
+ wire z = A.B.C.x;
+ end
+ assign A.x = A.B.C.x;
+ end
+ assign B.C.x = B.x;
+ end
+ end
+ endgenerate
+ assign x = Z.A.x;
+endmodule
diff --git a/tests/simple/genblk_order.v b/tests/simple/genblk_order.v
new file mode 100644
index 000000000..7c3a7a756
--- /dev/null
+++ b/tests/simple/genblk_order.v
@@ -0,0 +1,18 @@
+`default_nettype none
+module top(
+ output wire out1,
+ output wire out2
+);
+ generate
+ if (1) begin : outer
+ if (1) begin : foo
+ wire x = 0;
+ if (1) begin : foo
+ wire x = 1;
+ assign out1 = foo.x;
+ end
+ assign out2 = foo.x;
+ end
+ end
+ endgenerate
+endmodule
diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v
new file mode 100644
index 000000000..a04631a20
--- /dev/null
+++ b/tests/simple/genblk_port_shadow.v
@@ -0,0 +1,10 @@
+module top(x);
+ generate
+ if (1) begin : blk
+ wire x;
+ assign x = 0;
+ end
+ endgenerate
+ output wire x;
+ assign x = blk.x;
+endmodule
diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index 12327b36e..445c88ba8 100644
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -167,7 +167,7 @@ module gen_test7;
reg [2:0] out2;
wire [2:0] out3;
generate
- begin : cond
+ if (1) begin : cond
reg [2:0] sub_out1;
reg [2:0] sub_out2;
wire [2:0] sub_out3;
@@ -215,9 +215,9 @@ module gen_test8;
wire [1:0] x = 2'b11;
generate
- begin : A
+ if (1) begin : A
wire [1:0] x;
- begin : B
+ if (1) begin : B
wire [1:0] x = 2'b00;
`ASSERT(x == 0)
`ASSERT(A.x == 2)
@@ -228,7 +228,7 @@ module gen_test8;
`ASSERT(gen_test8.A.C.x == 1)
`ASSERT(gen_test8.A.B.x == 0)
end
- begin : C
+ if (1) begin : C
wire [1:0] x = 2'b01;
`ASSERT(x == 1)
`ASSERT(A.x == 2)
@@ -260,3 +260,66 @@ module gen_test8;
`ASSERT(gen_test8.A.C.x == 1)
`ASSERT(gen_test8.A.B.x == 0)
endmodule
+
+// ------------------------------------------
+
+module gen_test9;
+
+// `define VERIFY
+`ifdef VERIFY
+ `define ASSERT(expr) assert property (expr);
+`else
+ `define ASSERT(expr)
+`endif
+
+ wire [1:0] w = 2'b11;
+ generate
+ begin : A
+ wire [1:0] x;
+ begin : B
+ wire [1:0] y = 2'b00;
+ `ASSERT(w == 3)
+ `ASSERT(x == 2)
+ `ASSERT(y == 0)
+ `ASSERT(A.x == 2)
+ `ASSERT(A.C.z == 1)
+ `ASSERT(A.B.y == 0)
+ `ASSERT(gen_test9.w == 3)
+ `ASSERT(gen_test9.A.x == 2)
+ `ASSERT(gen_test9.A.C.z == 1)
+ `ASSERT(gen_test9.A.B.y == 0)
+ end
+ begin : C
+ wire [1:0] z = 2'b01;
+ `ASSERT(w == 3)
+ `ASSERT(x == 2)
+ `ASSERT(z == 1)
+ `ASSERT(A.x == 2)
+ `ASSERT(A.C.z == 1)
+ `ASSERT(A.B.y == 0)
+ `ASSERT(gen_test9.w == 3)
+ `ASSERT(gen_test9.A.x == 2)
+ `ASSERT(gen_test9.A.C.z == 1)
+ `ASSERT(gen_test9.A.B.y == 0)
+ end
+ assign x = B.y ^ 2'b11 ^ C.z;
+ `ASSERT(x == 2)
+ `ASSERT(A.x == 2)
+ `ASSERT(A.C.z == 1)
+ `ASSERT(A.B.y == 0)
+ `ASSERT(gen_test9.w == 3)
+ `ASSERT(gen_test9.A.x == 2)
+ `ASSERT(gen_test9.A.C.z == 1)
+ `ASSERT(gen_test9.A.B.y == 0)
+ end
+ endgenerate
+
+ `ASSERT(w == 3)
+ `ASSERT(A.x == 2)
+ `ASSERT(A.C.z == 1)
+ `ASSERT(A.B.y == 0)
+ `ASSERT(gen_test9.w == 3)
+ `ASSERT(gen_test9.A.x == 2)
+ `ASSERT(gen_test9.A.C.z == 1)
+ `ASSERT(gen_test9.A.B.y == 0)
+endmodule
diff --git a/tests/simple/local_loop_var.sv b/tests/simple/local_loop_var.sv
new file mode 100644
index 000000000..46b4e5c22
--- /dev/null
+++ b/tests/simple/local_loop_var.sv
@@ -0,0 +1,11 @@
+module top(out);
+ output integer out;
+ initial begin
+ integer i;
+ for (i = 0; i < 5; i = i + 1)
+ if (i == 0)
+ out = 1;
+ else
+ out += 2 ** i;
+ end
+endmodule
diff --git a/tests/simple/loop_var_shadow.v b/tests/simple/loop_var_shadow.v
new file mode 100644
index 000000000..0222a4493
--- /dev/null
+++ b/tests/simple/loop_var_shadow.v
@@ -0,0 +1,15 @@
+module top(out);
+ genvar i;
+ generate
+ for (i = 0; i < 2; i = i + 1) begin : loop
+ localparam j = i + 1;
+ if (1) begin : blk
+ localparam i = j + 1;
+ wire [i:0] x;
+ assign x = 1'sb1;
+ end
+ end
+ endgenerate
+ output wire [63:0] out;
+ assign out = {loop[0].blk.x, loop[1].blk.x};
+endmodule
diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv
new file mode 100644
index 000000000..75c4cd136
--- /dev/null
+++ b/tests/simple/macro_arg_spaces.sv
@@ -0,0 +1,28 @@
+module top(
+ input wire [31:0] i,
+ output wire [31:0] x, y, z
+);
+
+`define BAR(a) a
+`define FOO(a = function automatic [31:0] f) a
+
+`BAR(function automatic [31:0] a);
+ input [31:0] i;
+ a = i * 2;
+endfunction
+
+`FOO();
+ input [31:0] i;
+ f = i * 3;
+endfunction
+
+`FOO(function automatic [31:0] b);
+ input [31:0] i;
+ b = i * 5;
+endfunction
+
+assign x = a(i);
+assign y = f(i);
+assign z = b(i);
+
+endmodule
diff --git a/tests/simple/macro_arg_surrounding_spaces.v b/tests/simple/macro_arg_surrounding_spaces.v
new file mode 100644
index 000000000..3dbb5ea01
--- /dev/null
+++ b/tests/simple/macro_arg_surrounding_spaces.v
@@ -0,0 +1,20 @@
+module top(
+ IDENT_V_,
+ IDENT_W_,
+ IDENT_X_,
+ IDENT_Y_,
+ IDENT_Z_,
+ IDENT_A_,
+ IDENT_B_,
+ IDENT_C_
+);
+ `define MACRO(dummy, x) IDENT_``x``_
+ output wire IDENT_V_;
+ output wire `MACRO(_,W);
+ output wire `MACRO(_, X);
+ output wire `MACRO(_,Y );
+ output wire `MACRO(_, Z );
+ output wire `MACRO(_, A);
+ output wire `MACRO(_,B );
+ output wire `MACRO(_, C );
+endmodule
diff --git a/tests/simple/named_genblk.v b/tests/simple/named_genblk.v
new file mode 100644
index 000000000..b8300fc4d
--- /dev/null
+++ b/tests/simple/named_genblk.v
@@ -0,0 +1,27 @@
+`default_nettype none
+module top;
+ generate
+ if (1) begin
+ wire t;
+ begin : foo
+ wire x;
+ end
+ wire u;
+ end
+ begin : bar
+ wire x;
+ wire y;
+ begin : baz
+ wire x;
+ wire z;
+ end
+ end
+ endgenerate
+ assign genblk1.t = 1;
+ assign genblk1.foo.x = 1;
+ assign genblk1.u = 1;
+ assign bar.x = 1;
+ assign bar.y = 1;
+ assign bar.baz.x = 1;
+ assign bar.baz.z = 1;
+endmodule
diff --git a/tests/simple/nested_genblk_resolve.v b/tests/simple/nested_genblk_resolve.v
new file mode 100644
index 000000000..da5593f8a
--- /dev/null
+++ b/tests/simple/nested_genblk_resolve.v
@@ -0,0 +1,14 @@
+`default_nettype none
+module top;
+ generate
+ if (1) begin
+ wire x;
+ genvar i;
+ for (i = 0; i < 1; i = i + 1) begin
+ if (1) begin
+ assign x = 1;
+ end
+ end
+ end
+ endgenerate
+endmodule
diff --git a/tests/simple/unnamed_block_decl.sv b/tests/simple/unnamed_block_decl.sv
new file mode 100644
index 000000000..e81b457a8
--- /dev/null
+++ b/tests/simple/unnamed_block_decl.sv
@@ -0,0 +1,17 @@
+module top(z);
+ output integer z;
+ initial begin
+ integer x;
+ x = 1;
+ begin
+ integer y;
+ y = x + 1;
+ begin
+ integer z;
+ z = y + 1;
+ y = z + 1;
+ end
+ z = y + 1;
+ end
+ end
+endmodule
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