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-rw-r--r--tests/simple/dynslice.v12
-rw-r--r--tests/simple/partsel.v4
2 files changed, 16 insertions, 0 deletions
diff --git a/tests/simple/dynslice.v b/tests/simple/dynslice.v
new file mode 100644
index 000000000..7236ac3a5
--- /dev/null
+++ b/tests/simple/dynslice.v
@@ -0,0 +1,12 @@
+module dynslice (
+ input clk ,
+ input [9:0] ctrl ,
+ input [15:0] din ,
+ input [3:0] sel ,
+ output reg [127:0] dout
+);
+always @(posedge clk)
+begin
+ dout[ctrl*sel+:16] <= din ;
+end
+endmodule
diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v
index 7461358ad..83493fcb0 100644
--- a/tests/simple/partsel.v
+++ b/tests/simple/partsel.v
@@ -60,3 +60,7 @@ always @(posedge clk) begin
end
endmodule
+
+module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
+assign dout = din[a*b +: 2];
+endmodule