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-rw-r--r--tests/simple/constmuldivmod.v27
-rw-r--r--tests/simple/dff_different_styles.v2
-rw-r--r--tests/simple/graphtest.v34
-rw-r--r--tests/simple/hierarchy.v4
-rw-r--r--tests/simple/loops.v6
-rw-r--r--tests/simple/mem2reg.v10
-rw-r--r--tests/simple/memory.v59
-rw-r--r--tests/simple/omsp_dbg_uart.v4
-rw-r--r--tests/simple/rotate.v2
-rw-r--r--tests/simple/task_func.v42
-rw-r--r--tests/simple/vloghammer.v4
-rw-r--r--tests/simple/wreduce.v9
12 files changed, 188 insertions, 15 deletions
diff --git a/tests/simple/constmuldivmod.v b/tests/simple/constmuldivmod.v
new file mode 100644
index 000000000..d1d8be862
--- /dev/null
+++ b/tests/simple/constmuldivmod.v
@@ -0,0 +1,27 @@
+module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y);
+ always @* begin
+ case (mode)
+ 0: Y = A / 8'd0;
+ 1: Y = A % 8'd0;
+ 2: Y = A * 8'd0;
+
+ 3: Y = A / 8'd1;
+ 4: Y = A % 8'd1;
+ 5: Y = A * 8'd1;
+
+ 6: Y = A / 8'd2;
+ 7: Y = A % 8'd2;
+ 8: Y = A * 8'd2;
+
+ 9: Y = A / 8'd4;
+ 10: Y = A % 8'd4;
+ 11: Y = A * 8'd4;
+
+ 12: Y = A / 8'd8;
+ 13: Y = A % 8'd8;
+ 14: Y = A * 8'd8;
+
+ default: Y = 8'd16 * A;
+ endcase
+ end
+endmodule
diff --git a/tests/simple/dff_different_styles.v b/tests/simple/dff_different_styles.v
index 2f2737c4c..7765d6e2a 100644
--- a/tests/simple/dff_different_styles.v
+++ b/tests/simple/dff_different_styles.v
@@ -65,7 +65,7 @@ always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
end
endmodule
-// SR-Flip-Flops are on the edge of well defined vewrilog constructs in terms of
+// SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of
// simulation-implementation mismatches. The following testcases try to cover the
// part that is defined and avoid the undefined cases.
diff --git a/tests/simple/graphtest.v b/tests/simple/graphtest.v
new file mode 100644
index 000000000..74788dbbe
--- /dev/null
+++ b/tests/simple/graphtest.v
@@ -0,0 +1,34 @@
+module graphtest (A,B,X,Y,Z);
+
+input [3:0] A;
+input [3:0] B;
+output reg [3:0] X;
+output [9:0] Y;
+output [7:0] Z;
+
+wire [4:0] t;
+
+assign t[4] = 1'b0; // Constant connects to wire
+assign t[2:0] = A[2:0] & { 2'b10, B[3]}; // Concatenation of intermediate wire
+assign t[3] = A[2] ^ B[3]; // Bitwise-XOR
+
+// assign Y[2:0] = 3'b111;
+// assign Y[6:3] = A;
+// assign Y[9:7] = t[0:2];
+assign Y = {3'b111, A, t[2:0]}; // Direct assignment of concatenation
+
+assign Z[0] = 1'b0; // Constant connects to PO
+assign Z[1] = t[3]; // Intermediate sig connects to PO
+assign Z[3:2] = A[2:1]; // PI connects to PO
+assign Z[7:4] = {1'b0, B[2:0]}; // Concat of CV and PI connect to PO
+
+always @* begin
+ if (A == 4'b1111) begin // All-Const at port (eq)
+ X = B;
+ end
+ else begin
+ X = 4'b0000; // All-Const at port (mux)
+ end
+end
+
+endmodule
diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v
index 17888009f..123afaeab 100644
--- a/tests/simple/hierarchy.v
+++ b/tests/simple/hierarchy.v
@@ -5,10 +5,10 @@ input [3:0] a;
input signed [3:0] b;
output [7:0] y1, y2, y3, y4;
-// this version triggers a bug in icarus verilog
+// this version triggers a bug in Icarus Verilog
// submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4);
-// this version is handled correctly by icarus verilog
+// this version is handled correctly by Icarus Verilog
submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
endmodule
diff --git a/tests/simple/loops.v b/tests/simple/loops.v
index 77cdcd8e2..d7743a422 100644
--- a/tests/simple/loops.v
+++ b/tests/simple/loops.v
@@ -41,10 +41,10 @@ begin
keysched_last_key_i = key_i;
else
keysched_last_key_i = keysched_new_key_o;
-
+
if (round == 0 && addroundkey_start_i)
begin
- data_var = addroundkey_data_i;
+ data_var = addroundkey_data_i;
round_key_var = key_i;
round_data_var = round_key_var ^ data_var;
next_addroundkey_data_reg = round_data_var;
@@ -66,7 +66,7 @@ begin
end
else if (addroundkey_round == round && keysched_ready_o)
begin
- data_var = addroundkey_data_i;
+ data_var = addroundkey_data_i;
round_key_var = keysched_new_key_o;
round_data_var = round_key_var ^ data_var;
next_addroundkey_data_reg = round_data_var;
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index bed5528d4..b1ab04d62 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -19,9 +19,9 @@ endmodule
// ------------------------------------------------------
-module mem2reg_test2(clk, mode, addr, data);
+module mem2reg_test2(clk, reset, mode, addr, data);
-input clk, mode;
+input clk, reset, mode;
input [2:0] addr;
output [3:0] data;
@@ -33,6 +33,10 @@ assign data = mem[addr];
integer i;
always @(posedge clk) begin
+ if (reset) begin
+ for (i=0; i<8; i=i+1)
+ mem[i] <= i;
+ end else
if (mode) begin
for (i=0; i<8; i=i+1)
mem[i] <= mem[i]+1;
@@ -47,7 +51,7 @@ endmodule
// http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
-reg [7:0] dint_c [0:7];
+reg [7:0] dint_c [0:7];
always @(posedge clk)
begin
{dout_a[0], dint_c[3]} <= din_a;
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index db06c56d2..9fddce26c 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -205,3 +205,62 @@ module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y);
end
endmodule
+// ----------------------------------------------------------
+
+module memtest09 (
+ input clk,
+ input [3:0] a_addr, a_din, b_addr, b_din,
+ input a_wen, b_wen,
+ output reg [3:0] a_dout, b_dout
+);
+ reg [3:0] memory [10:35];
+
+ always @(posedge clk) begin
+ if (a_wen)
+ memory[10 + a_addr] <= a_din;
+ a_dout <= memory[10 + a_addr];
+ end
+
+ always @(posedge clk) begin
+ if (b_wen && (10 + a_addr != 20 + b_addr || !a_wen))
+ memory[20 + b_addr] <= b_din;
+ b_dout <= memory[20 + b_addr];
+ end
+endmodule
+
+// ----------------------------------------------------------
+
+module memtest10(input clk, input [5:0] din, output [5:0] dout);
+ reg [5:0] queue [0:3];
+ integer i;
+
+ always @(posedge clk) begin
+ queue[0] <= din;
+ for (i = 1; i < 4; i=i+1) begin
+ queue[i] <= queue[i-1];
+ end
+ end
+
+ assign dout = queue[3];
+endmodule
+
+// ----------------------------------------------------------
+
+module memtest11(clk, wen, waddr, raddr, wdata, rdata);
+ input clk, wen;
+ input [1:0] waddr, raddr;
+ input [7:0] wdata;
+ output [7:0] rdata;
+
+ reg [7:0] mem [3:0];
+
+ assign rdata = mem[raddr];
+
+ always @(posedge clk) begin
+ if (wen)
+ mem[waddr] <= wdata;
+ else
+ mem[waddr] <= mem[waddr];
+ end
+endmodule
+
diff --git a/tests/simple/omsp_dbg_uart.v b/tests/simple/omsp_dbg_uart.v
index dc8860dee..569a28adb 100644
--- a/tests/simple/omsp_dbg_uart.v
+++ b/tests/simple/omsp_dbg_uart.v
@@ -22,13 +22,13 @@ always @(uart_state or mem_burst)
RX_DATA : uart_state_nxt = RX_SYNC;
default : uart_state_nxt = RX_CMD;
endcase
-
+
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) uart_state <= RX_SYNC;
else if (xfer_done | mem_burst) uart_state <= uart_state_nxt;
assign cmd_valid = (uart_state==RX_CMD) & xfer_done;
assign xfer_done = uart_state!=RX_SYNC;
-
+
endmodule
diff --git a/tests/simple/rotate.v b/tests/simple/rotate.v
index eb832e6f5..a2fe00055 100644
--- a/tests/simple/rotate.v
+++ b/tests/simple/rotate.v
@@ -1,5 +1,5 @@
-// test case taken from amber23 verilog code
+// test case taken from amber23 Verilog code
module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod);
input [31:0] i_in;
diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v
index 9b8e26e51..fa50c1d5c 100644
--- a/tests/simple/task_func.v
+++ b/tests/simple/task_func.v
@@ -68,7 +68,7 @@ endmodule
// -------------------------------------------------------------------
-module task_func_test03( input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a);
+module task_func_test03(input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a);
assign dout_a = test(din_a,din_b);
function [7:0] test;
input [7:0] a;
@@ -80,3 +80,43 @@ module task_func_test03( input [7:0] din_a, input [7:0] din_b, output [7:0] dout
end
endfunction
endmodule
+
+// -------------------------------------------------------------------
+
+module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4);
+ parameter p = 23;
+ parameter px = 42;
+ function [7:0] test1;
+ input [7:0] i;
+ parameter p = 42;
+ begin
+ test1 = i + p;
+ end
+ endfunction
+ function [7:0] test2;
+ input [7:0] i;
+ parameter p2 = p+42;
+ begin
+ test2 = i + p2;
+ end
+ endfunction
+ function [7:0] test3;
+ input [7:0] i;
+ begin
+ test3 = i + p;
+ end
+ endfunction
+ function [7:0] test4;
+ input [7:0] i;
+ parameter px = p + 13;
+ parameter p3 = px - 37;
+ parameter p4 = p3 ^ px;
+ begin
+ test4 = i + p4;
+ end
+ endfunction
+ assign out1 = test1(in);
+ assign out2 = test2(in);
+ assign out3 = test3(in);
+ assign out4 = test4(in);
+endmodule
diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v
index d1f55fdb4..3bb3cf992 100644
--- a/tests/simple/vloghammer.v
+++ b/tests/simple/vloghammer.v
@@ -27,14 +27,14 @@ module test04(a, y);
assign y = ~(a - 1'b0);
endmodule
-// .. this test triggers a bug in xilinx isim.
+// .. this test triggers a bug in Xilinx ISIM.
// module test05(a, y);
// input a;
// output y;
// assign y = 12345 >> {a, 32'd0};
// endmodule
-// .. this test triggers a bug in icarus verilog.
+// .. this test triggers a bug in Icarus Verilog.
// module test06(a, b, c, y);
// input signed [3:0] a;
// input signed [1:0] b;
diff --git a/tests/simple/wreduce.v b/tests/simple/wreduce.v
new file mode 100644
index 000000000..ba5484385
--- /dev/null
+++ b/tests/simple/wreduce.v
@@ -0,0 +1,9 @@
+module wreduce_test0(input [7:0] a, b, output [15:0] x, y, z);
+ assign x = -$signed({1'b0, a});
+ assign y = $signed({1'b0, a}) + $signed({1'b0, b});
+ assign z = x ^ y;
+endmodule
+
+module wreduce_test1(input [31:0] a, b, output [7:0] x, y, z, w);
+ assign x = a - b, y = a * b, z = a >> b, w = a << b;
+endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-12 15:26:01 +0000