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Diffstat (limited to 'tests/techmap/dfflegalize_adlatch_init.ys')
| -rw-r--r-- | tests/techmap/dfflegalize_adlatch_init.ys | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/tests/techmap/dfflegalize_adlatch_init.ys b/tests/techmap/dfflegalize_adlatch_init.ys new file mode 100644 index 000000000..a55082d1d --- /dev/null +++ b/tests/techmap/dfflegalize_adlatch_init.ys @@ -0,0 +1,99 @@ +read_verilog -icells <<EOT + +module adlatch0(input E, R, D, (* init = 3'b000 *) output [2:0] Q); +$_DLATCH_PP0_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0])); +$_DLATCH_PN0_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1])); +$_DLATCH_NP0_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2])); +endmodule + +module adlatch1(input E, R, D, (* init = 3'b000 *) output [2:0] Q); +$_DLATCH_PP1_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0])); +$_DLATCH_PN1_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1])); +$_DLATCH_NP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2])); +endmodule + +module top(input C, E, R, D, output [13:0] Q); +adlatch0 adlatch0_(.E(E), .R(R), .D(D), .Q(Q[2:0])); +adlatch1 adlatch1_(.E(E), .R(R), .D(D), .Q(Q[5:3])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 0 + +select -assert-count 2 adlatch0/t:$_NOT_ +select -assert-count 10 adlatch1/t:$_NOT_ +select -assert-count 0 adlatch0/t:$_MUX_ +select -assert-count 3 adlatch1/t:$_MUX_ +select -assert-count 3 adlatch0/t:$_DLATCH_PP0_ +select -assert-count 9 adlatch1/t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 1 + +select -assert-count 13 adlatch0/t:$_NOT_ +select -assert-count 8 adlatch1/t:$_NOT_ +select -assert-count 3 adlatch0/t:$_MUX_ +select -assert-count 0 adlatch1/t:$_MUX_ +select -assert-count 9 adlatch0/t:$_DLATCH_PP0_ +select -assert-count 3 adlatch1/t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 0 + +select -assert-count 10 adlatch0/t:$_NOT_ +select -assert-count 2 adlatch1/t:$_NOT_ +select -assert-count 3 adlatch0/t:$_MUX_ +select -assert-count 0 adlatch1/t:$_MUX_ +select -assert-count 9 adlatch0/t:$_DLATCH_PP1_ +select -assert-count 3 adlatch1/t:$_DLATCH_PP1_ +select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 1 + +select -assert-count 8 adlatch0/t:$_NOT_ +select -assert-count 13 adlatch1/t:$_NOT_ +select -assert-count 0 adlatch0/t:$_MUX_ +select -assert-count 3 adlatch1/t:$_MUX_ +select -assert-count 3 adlatch0/t:$_DLATCH_PP1_ +select -assert-count 9 adlatch1/t:$_DLATCH_PP1_ +select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 0 + +select -assert-count 2 adlatch0/t:$_NOT_ +select -assert-count 2 adlatch1/t:$_NOT_ +select -assert-count 0 adlatch0/t:$_MUX_ +select -assert-count 0 adlatch1/t:$_MUX_ +select -assert-count 6 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 1 + +select -assert-count 8 adlatch0/t:$_NOT_ +select -assert-count 8 adlatch1/t:$_NOT_ +select -assert-count 0 adlatch0/t:$_MUX_ +select -assert-count 0 adlatch1/t:$_MUX_ +select -assert-count 6 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i |