1 files changed, 64 insertions, 0 deletions
diff --git a/tests/techmap/dfflegalize_dlatch.ys b/tests/techmap/dfflegalize_dlatch.ys
new file mode 100644
index 000000000..11683bc1a
--- /dev/null
+++ b/tests/techmap/dfflegalize_dlatch.ys
@@ -0,0 +1,64 @@
+read_verilog -icells <<EOT
+
+module dlatch(input E, D, output [1:0] Q);
+$_DLATCH_P_ ff0 (.E(E), .D(D), .Q(Q[0]));
+$_DLATCH_N_ ff1 (.E(E), .D(D), .Q(Q[1]));
+endmodule
+
+EOT
+
+design -save orig
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x
+equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x
+
+# Convert everything to DFFs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_P_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_DLATCH_P_
+select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ADLATCHs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_DLATCH_PP0_
+select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to DLATCHSRs.
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_DLATCHSR_PPP_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ALDFFs.
+
+design -load orig
+dfflegalize -cell $_ALDFF_PP_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_ALDFF_PP_
+select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ALDFFEs.
+
+design -load orig
+dfflegalize -cell $_ALDFFE_PPP_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_ALDFFE_PPP_
+select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i