2 files changed, 76 insertions, 2 deletions
diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys
index c058d1607..25ea94dfc 100644
--- a/tests/techmap/iopadmap.ys
+++ b/tests/techmap/iopadmap.ys
@@ -4,12 +4,15 @@ module obuf (input i, (* iopad_external_pin *) output o); endmodule
 module obuft (input i, input oe, (* iopad_external_pin *) output o); endmodule
 module iobuf (input i, input oe, output o, (* iopad_external_pin *) inout io); endmodule
 
+module buf_inside (input i, output o);
+obuf b (.i(i), .o(o));
+endmodule
+
 module a(input i, output o);
 assign o = i;
 endmodule
 
 module b(input i, output o);
-assign o = i;
 ibuf b (.i(i), .o(o));
 endmodule
 
@@ -42,12 +45,22 @@ assign io = i;
 assign o = io;
 endmodule
 
+module i(input i, output o);
+buf_inside b (.i(i), .o(o));
+endmodule
+
+module j(input i, output o);
+wire tmp;
+obuf b (.i(i), .o(tmp));
+assign o = tmp;
+endmodule
+
 EOT
 
 opt_clean
 tribuf
 simplemap
-iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io
+iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io a b c d e f g h i j
 opt_clean
 
 select -assert-count 1 a/t:ibuf
@@ -120,3 +133,46 @@ select -assert-count 1 g/t:iobuf
 select -assert-count 1 h/t:ibuf
 select -assert-count 1 h/t:iobuf
 select -assert-count 1 h/t:obuf
+
+select -assert-count 1 i/t:ibuf
+select -assert-count 0 i/t:obuf
+
+select -assert-count 1 j/t:ibuf
+select -assert-count 1 j/t:obuf
+
+
+# Check that \init attributes get moved from output buffer
+#   to buffer input
+design -reset
+read_verilog << EOT
+module obuf (input i, (* iopad_external_pin *) output o); endmodule
+module obuft (input i, input oe, (* iopad_external_pin *) output o); endmodule
+module iobuf (input i, input oe, output o, (* iopad_external_pin *) inout io); endmodule
+module sub(input i, output o); endmodule
+
+module a(input i, (* init=1'b1 *) output o);
+sub s(.i(i), .o(o));
+endmodule
+
+module b(input [1:0] i, oe, (* init=2'b1x *) output [1:0] o);
+wire [1:0] w;
+sub s1(.i(i[0]), .o(w[0]));
+sub s2(.i(i[1]), .o(w[1]));
+assign o = oe ? w : 2'bz;
+endmodule
+
+module c(input i, oe, (* init=2'b00 *) inout io, output o1, o2);
+assign io = oe ? i : 1'bz;
+assign {o1,o2} = {io,io};
+endmodule
+EOT
+opt_clean
+tribuf
+simplemap
+iopadmap -bits -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io
+select -assert-count 1 a/c:s %co a/a:init=1'b1 %i
+select -assert-count 1 a/a:init
+select -assert-count 1 b/c:s* %co %a b/a:init=2'b1x %i
+select -assert-count 1 b/a:init
+select -assert-count 1 c/t:iobuf %co c/a:init=2'b00 %i
+select -assert-count 1 c/a:init
diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index c2f42d50b..8403586bd 100644
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -16,3 +16,21 @@ EOT
 techmap -map %techmap
 select -assert-any w:s0.asdf
 select -assert-any c:s0.blah
+
+read_verilog <<EOT
+module sub(input i, output o, input j);
+wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+select -assert-any w:s0.asdf
+select -assert-any c:s0.blah