4 files changed, 188 insertions, 1 deletions
diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys
index 62b5dfef6..2140dde26 100644
--- a/tests/techmap/abc9.ys
+++ b/tests/techmap/abc9.ys
@@ -39,6 +39,35 @@ design -load gold
 scratchpad -copy abc9.script.flow3 abc9.script
 abc9 -lut 4
 
+design -reset
+read_verilog <<EOT
+module top(input a, b, output o);
+(* keep *) wire w = a & b;
+assign o = ~w;
+endmodule
+EOT
+
+simplemap
+equiv_opt -assert abc9 -lut 4
+design -load postopt
+select -assert-count 2 t:$lut
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input a, b, output o);
+wire w;
+(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b));
+assign o = ~w;
+endmodule
+EOT
+
+simplemap
+equiv_opt -assert abc9 -lut 4
+design -load postopt
+select -assert-count 1 t:$lut
+select -assert-count 1 t:$_AND_
+
 
 design -reset
 read_verilog -icells <<EOT
diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys
index c058d1607..0bcc71cce 100644
--- a/tests/techmap/iopadmap.ys
+++ b/tests/techmap/iopadmap.ys
@@ -120,3 +120,40 @@ select -assert-count 1 g/t:iobuf
 select -assert-count 1 h/t:ibuf
 select -assert-count 1 h/t:iobuf
 select -assert-count 1 h/t:obuf
+
+
+# Check that \init attributes get moved from output buffer
+#   to buffer input
+design -reset
+read_verilog << EOT
+module obuf (input i, (* iopad_external_pin *) output o); endmodule
+module obuft (input i, input oe, (* iopad_external_pin *) output o); endmodule
+module iobuf (input i, input oe, output o, (* iopad_external_pin *) inout io); endmodule
+module sub(input i, output o); endmodule
+
+module a(input i, (* init=1'b1 *) output o);
+sub s(.i(i), .o(o));
+endmodule
+
+module b(input [1:0] i, oe, (* init=2'b1x *) output [1:0] o);
+wire [1:0] w;
+sub s1(.i(i[0]), .o(w[0]));
+sub s2(.i(i[1]), .o(w[1]));
+assign o = oe ? w : 2'bz;
+endmodule
+
+module c(input i, oe, (* init=2'b00 *) inout io, output o1, o2);
+assign io = oe ? i : 1'bz;
+assign {o1,o2} = {io,io};
+endmodule
+EOT
+opt_clean
+tribuf
+simplemap
+iopadmap -bits -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io
+select -assert-count 1 a/c:s %co a/a:init=1'b1 %i
+select -assert-count 1 a/a:init
+select -assert-count 1 b/c:s* %co %a b/a:init=2'b1x %i
+select -assert-count 1 b/a:init
+select -assert-count 1 c/t:iobuf %co c/a:init=2'b00 %i
+select -assert-count 1 c/a:init
diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh
index 96489ff15..c16f204d9 100755
--- a/tests/techmap/run-test.sh
+++ b/tests/techmap/run-test.sh
@@ -6,7 +6,7 @@ for x in *.ys; do
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log $x"
+	echo "	@../../yosys -ql ${x%.ys}.log -e 'select out of bounds' $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys
new file mode 100644
index 000000000..eb29680f6
--- /dev/null
+++ b/tests/techmap/shiftx2mux.ys
@@ -0,0 +1,121 @@
+read_verilog <<EOT
+module sc1 (i1 ,
+            i2 ,
+            i3 ,
+            i4 ,
+            i5 ,
+            i6 ,
+            i7 ,
+            i8 ,
+            i9 ,
+            i10,
+            i11,
+            i12,
+            i13,
+            i14,
+            i15,
+            binary_out,
+            encoder_in,
+            enable
+);
+
+input [3:0]   i1 ;
+input [3:0]   i2 ;
+input [3:0]   i3 ;
+input [3:0]   i4 ;
+input [3:0]   i5 ;
+input [3:0]   i6 ;
+input [3:0]   i7 ;
+input [3:0]   i8 ;
+input [3:0]   i9 ;
+input [3:0]   i10 ;
+input [3:0]   i11 ;
+input [3:0]   i12 ;
+input [3:0]   i13 ;
+input [3:0]   i14 ;
+input [3:0]   i15 ;
+
+output reg [3:0] binary_out  ;
+
+input [3:0] encoder_in ;
+input  enable ;
+
+
+
+always @ (*)
+begin
+	binary_out = 0;
+	if (enable) begin
+		case (encoder_in)
+			4'h1 : binary_out = i1;
+			4'h2 : binary_out = i2;
+			4'h3 : binary_out = i3;
+			4'h4 : binary_out = i4;
+			4'h5 : binary_out = i5;
+			4'h6 : binary_out = i6;
+			4'h7 : binary_out = i7;
+			4'h8 : binary_out = i8;
+			4'h9 : binary_out = i9;
+			4'ha : binary_out = i10;
+			4'hb : binary_out = i11;/*
+			4'hc : binary_out = i12;
+			4'hd : binary_out = i13;
+			4'he : binary_out = i14;
+			4'hf : binary_out = i15;*/
+	       endcase
+       end
+end
+endmodule
+EOT
+
+proc
+pmux2shiftx
+design -save gold
+
+
+design -load gold
+techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
+abc -lut 6
+select -assert-min 17 t:$lut
+
+
+design -load gold
+techmap
+abc -lut 6
+select -assert-count 16 t:$lut
+
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+
+design -load gold
+techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
+abc9 -lut 6
+select -assert-min 17 t:$lut
+
+
+design -load gold
+techmap
+abc9 -lut 6
+select -assert-count 16 t:$lut
+
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+
+design -reset
+read_verilog <<EOT
+module top(input [6:0] A, input [1:0] B, output [1:0] Y);
+wire [7:0] AA = {1'bx, A};
+assign Y = AA[B*2 +: 2];
+endmodule
+EOT
+opt
+wreduce
+equiv_opt techmap