diff options
Diffstat (limited to 'tests/techmap')
41 files changed, 4026 insertions, 91 deletions
diff --git a/tests/techmap/adff2dff.ys b/tests/techmap/adff2dff.ys new file mode 100644 index 000000000..53f7d2f08 --- /dev/null +++ b/tests/techmap/adff2dff.ys @@ -0,0 +1,19 @@ +read_verilog -icells << EOT +module top(...); + +input [1:0] D; +input C, R; +output [1:0] Q; + +always @(posedge C, posedge R) + if (R) + Q <= 0; + else + Q <= D; + +endmodule +EOT + +proc + +equiv_opt -async2sync techmap -map +/adff2dff.v diff --git a/tests/techmap/bug2183.ys b/tests/techmap/bug2183.ys new file mode 100644 index 000000000..8dd09458e --- /dev/null +++ b/tests/techmap/bug2183.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module foo(inout a, b); + assign a = b; +endmodule +module bar(output c); + foo f(c, 1'b0); +endmodule +EOT + +hierarchy -auto-top +flatten diff --git a/tests/techmap/bug2321.ys b/tests/techmap/bug2321.ys new file mode 100644 index 000000000..637528b21 --- /dev/null +++ b/tests/techmap/bug2321.ys @@ -0,0 +1,15 @@ +read_verilog <<EOT +module m (input i, output o); +wire [1023:0] _TECHMAP_DO_00_ = "CONSTMAP; "; +endmodule +EOT + +design -stash map + +read_verilog <<EOT +module top(output o); +m m (.o(o), .i(o)); +endmodule +EOT + +techmap -map %map diff --git a/tests/techmap/bug2332.ys b/tests/techmap/bug2332.ys new file mode 100644 index 000000000..ed6b35eb2 --- /dev/null +++ b/tests/techmap/bug2332.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module top(input [31:0] a, input signed [2:0] x, output [2:0] o); + +wire [5:0] t = x * 3; +assign o = a >> t; + +endmodule +EOT + +wreduce +equiv_opt -assert peepopt diff --git a/tests/techmap/bug2759.ys b/tests/techmap/bug2759.ys new file mode 100644 index 000000000..05699bef8 --- /dev/null +++ b/tests/techmap/bug2759.ys @@ -0,0 +1,14 @@ +read_verilog -specify <<EOT +(* abc9_box, whitebox *) +module box(input [1:0] i, output o); +specify +(i *> o) = 1; +endspecify +assign o = ^i; +endmodule + +module top(input [1:0] i, output o); +box i1(i, o); +endmodule +EOT +abc9 -lut 4 diff --git a/tests/techmap/bug2972.ys b/tests/techmap/bug2972.ys new file mode 100644 index 000000000..8ae895f56 --- /dev/null +++ b/tests/techmap/bug2972.ys @@ -0,0 +1,20 @@ +read_verilog -specify <<EOT +(* abc9_box, blackbox*) +module box(input clk, d, output reg q, output do); +parameter P = 0; +always @(posedge clk) + q <= d; +assign do = d; +specify + (posedge clk => (q : d)) = 1; + (d => do) = 1; +endspecify +endmodule + +module top(input clk, d, output q); +box i1(clk, d, q); +endmodule +EOT +hierarchy +abc9 -lut 4 +abc9 -lut 4 diff --git a/tests/techmap/cellname.ys b/tests/techmap/cellname.ys new file mode 100644 index 000000000..2edd6a9fd --- /dev/null +++ b/tests/techmap/cellname.ys @@ -0,0 +1,41 @@ +read_verilog << EOT + +module sub (input i, output o); +parameter _TECHMAP_CELLNAME_ = ""; +namedsub #(.name(_TECHMAP_CELLNAME_)) _TECHMAP_REPLACE_ (i, o); +endmodule + +EOT + +design -stash map + +read_verilog << EOT + +(* blackbox *) +module sub (input i, output o); +endmodule + +(* blackbox *) +module namedsub (input i, output o); +parameter name = ""; +endmodule + +module top(input [3:0] i, output [3:0] o); + +sub s1 (i[0], o[0]); +sub subsubsub (i[1], o[1]); +sub s2 (i[2], o[2]); +sub xxx (i[3], o[3]); + +endmodule + +EOT + +techmap -map %map + +select -assert-count 4 t:namedsub +select -assert-count 0 t:sub +select -assert-count 1 t:namedsub r:name=s1 %i +select -assert-count 1 t:namedsub r:name=subsubsub %i +select -assert-count 1 t:namedsub r:name=s2 %i +select -assert-count 1 t:namedsub r:name=xxx %i diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys index b81a35e74..abe830109 100644 --- a/tests/techmap/clkbufmap.ys +++ b/tests/techmap/clkbufmap.ys @@ -1,5 +1,7 @@ read_verilog <<EOT module clkbuf (input i, (* clkbuf_driver *) output o); endmodule +module inbuf (input i, output o); endmodule +module clkinbuf (input i, (* clkbuf_driver *) output o); endmodule module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule module latch (input e, d, output q); endmodule @@ -105,3 +107,80 @@ select -assert-count 0 w:clk1 %a %co t:clkbuf %i select -assert-count 0 w:clk2 %a %co t:clkbuf %i select -assert-count 0 top/t:clkbuf select -assert-count 2 sub/t:clkbuf + +# ---------------------- + +design -load ref +clkbufmap -buf clkbuf o:i -inpad inbuf o:i +select -assert-count 3 top/t:clkbuf +select -assert-count 3 sub/t:clkbuf +select -assert-count 2 top/t:inbuf +select -assert-count 0 sub/t:inbuf +select -set clk1 w:clk1 %a %co t:inbuf %i +select -assert-count 1 @clk1 +select -assert-count 1 @clk1 %x:+[o] %co t:clkbuf %i +select -set clk1b @clk1 %x:+[o] %co t:clkbuf %i +select -assert-count 1 @clk1b %x:+[o] %co c:s* %i +select -assert-count 1 @clk1b %x:+[o] %co c:s0 %i +select -set clk2 w:clk2 %a %co t:inbuf %i +select -assert-count 1 @clk2 +select -assert-count 1 @clk2 %x:+[o] %co t:clkbuf %i +select -set clk2b @clk2 %x:+[o] %co t:clkbuf %i +select -assert-count 1 @clk2b %x:+[o] %co c:s* %i +select -assert-count 1 @clk2b %x:+[o] %co c:s1 %i +select -set clk5 w:clk5 %a %ci t:clkbuf %i +select -assert-count 1 @clk5 +select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i +select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i +select -set sclk4 w:sclk4 %a %ci t:clkbuf %i +select -assert-count 1 @sclk4 +select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i +select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i +select -set sclk8 w:sclk8 %a %ci t:clkbuf %i +select -assert-count 1 @sclk8 +select -assert-count 1 @sclk8 %x:+[o] %co c:s13 %i +select -assert-count 1 @sclk8 %x:+[i] %ci c:s12 %i + +# ---------------------- + +design -load ref +clkbufmap -inpad inbuf o:i +select -assert-count 2 top/t:inbuf +select -assert-count 0 sub/t:inbuf +select -set clk1 w:clk1 %a %co t:inbuf %i +select -assert-count 1 @clk1 +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i +select -set clk2 w:clk2 %a %co t:inbuf %i +select -assert-count 1 @clk2 +select -assert-count 1 @clk2 %x:+[o] %co c:s* %i +select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i + +# ---------------------- + +design -load ref +clkbufmap -buf clkbuf o:i -inpad clkinbuf o:i +select -assert-count 1 top/t:clkbuf +select -assert-count 3 sub/t:clkbuf +select -assert-count 2 top/t:clkinbuf +select -assert-count 0 sub/t:clkinbuf +select -set clk1 w:clk1 %a %co t:clkinbuf %i +select -assert-count 1 @clk1 +select -assert-count 1 @clk1 %x:+[o] %co c:s* %i +select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i +select -set clk2 w:clk2 %a %co t:clkinbuf %i +select -assert-count 1 @clk2 +select -assert-count 1 @clk2 %x:+[o] %co c:s* %i +select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i +select -set clk5 w:clk5 %a %ci t:clkbuf %i +select -assert-count 1 @clk5 +select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i +select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i +select -set sclk4 w:sclk4 %a %ci t:clkbuf %i +select -assert-count 1 @sclk4 +select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i +select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i +select -set sclk8 w:sclk8 %a %ci t:clkbuf %i +select -assert-count 1 @sclk8 +select -assert-count 1 @sclk8 %x:+[o] %co c:s13 %i +select -assert-count 1 @sclk8 %x:+[i] %ci c:s12 %i diff --git a/tests/techmap/dff2dffs.ys b/tests/techmap/dff2dffs.ys deleted file mode 100644 index 105a89400..000000000 --- a/tests/techmap/dff2dffs.ys +++ /dev/null @@ -1,50 +0,0 @@ -read_verilog << EOT -module top(...); -input clk; -input d; -input sr; -output reg q0, q1, q2, q3, q4, q5; - -initial q0 = 1'b0; -initial q1 = 1'b0; -initial q2 = 1'b1; -initial q3 = 1'b1; -initial q4 = 1'bx; -initial q5 = 1'bx; - -always @(posedge clk) begin - q0 <= sr ? 1'b0 : d; - q1 <= sr ? 1'b1 : d; - q2 <= sr ? 1'b0 : d; - q3 <= sr ? 1'b1 : d; - q4 <= sr ? 1'b0 : d; - q5 <= sr ? 1'b1 : d; -end - -endmodule -EOT - -proc -simplemap -design -save ref - -dff2dffs -clean - -select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q1 %x t:$_SDFF_PP1_ %i -select -assert-count 1 w:q2 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i -select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i - -design -load ref -dff2dffs -match-init -clean - -select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i -select -assert-count 0 w:q1 %x t:$_SDFF_PP1_ %i -select -assert-count 0 w:q2 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i -select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i diff --git a/tests/techmap/dff2ff.ys b/tests/techmap/dff2ff.ys new file mode 100644 index 000000000..5adf14b07 --- /dev/null +++ b/tests/techmap/dff2ff.ys @@ -0,0 +1,16 @@ +read_verilog -icells << EOT +module top(...); + +input [1:0] D; +input C; +output [1:0] Q; + +always @(posedge C) + Q <= D; + +endmodule +EOT + +proc + +equiv_opt techmap -map +/dff2ff.v diff --git a/tests/techmap/dfflegalize_adff.ys b/tests/techmap/dfflegalize_adff.ys new file mode 100644 index 000000000..fc579e7d6 --- /dev/null +++ b/tests/techmap/dfflegalize_adff.ys @@ -0,0 +1,135 @@ +read_verilog -icells <<EOT + +module adff0(input C, R, D, output [2:0] Q); +$_DFF_PP0_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0])); +$_DFF_PN0_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1])); +$_DFF_NP0_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2])); +endmodule + +module adff1(input C, R, D, output [2:0] Q); +$_DFF_PP1_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0])); +$_DFF_PN1_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1])); +$_DFF_NP1_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2])); +endmodule + +module adffe0(input C, E, R, D, output [3:0] Q); +$_DFFE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_DFFE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_DFFE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_DFFE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module adffe1(input C, E, R, D, output [3:0] Q); +$_DFFE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_DFFE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_DFFE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_DFFE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module top(input C, E, R, D, output [13:0] Q); +adff0 adff0_(.C(C), .R(R), .D(D), .Q(Q[2:0])); +adff1 adff1_(.C(C), .R(R), .D(D), .Q(Q[5:3])); +adffe0 adffe0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[9:6])); +adffe1 adffe1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[13:10])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x + + +# Convert everything to ADFFs. + +design -load orig +dfflegalize -cell $_DFF_PP0_ x + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 8 adff1/t:$_NOT_ +select -assert-count 2 adffe0/t:$_NOT_ +select -assert-count 10 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 14 t:$_DFF_PP0_ +select -assert-none t:$_DFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ADFFEs. + +design -load orig +dfflegalize -cell $_DFFE_PP0P_ x + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 8 adff1/t:$_NOT_ +select -assert-count 3 adffe0/t:$_NOT_ +select -assert-count 11 adffe1/t:$_NOT_ +select -assert-count 14 t:$_DFFE_PP0P_ +select -assert-none t:$_DFFE_PP0P_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ x + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 2 adffe0/t:$_NOT_ +select -assert-count 2 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 14 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ x + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 3 adffe0/t:$_NOT_ +select -assert-count 3 adffe1/t:$_NOT_ +select -assert-count 14 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ x + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 2 adffe0/t:$_NOT_ +select -assert-count 2 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 14 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ x + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 3 adffe0/t:$_NOT_ +select -assert-count 3 adffe1/t:$_NOT_ +select -assert-count 14 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_adff_init.ys b/tests/techmap/dfflegalize_adff_init.ys new file mode 100644 index 000000000..25ed59307 --- /dev/null +++ b/tests/techmap/dfflegalize_adff_init.ys @@ -0,0 +1,333 @@ +read_verilog -icells <<EOT + +module adff0(input C, R, D, (* init = 3'b000 *) output [2:0] Q); +$_DFF_PP0_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0])); +$_DFF_PN0_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1])); +$_DFF_NP0_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2])); +endmodule + +module adff1(input C, R, D, (* init = 3'b000 *) output [2:0] Q); +$_DFF_PP1_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0])); +$_DFF_PN1_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1])); +$_DFF_NP1_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2])); +endmodule + +module adffe0(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q); +$_DFFE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_DFFE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_DFFE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_DFFE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module adffe1(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q); +$_DFFE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_DFFE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_DFFE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_DFFE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module top(input C, E, R, D, output [13:0] Q); +adff0 adff0_(.C(C), .R(R), .D(D), .Q(Q[2:0])); +adff1 adff1_(.C(C), .R(R), .D(D), .Q(Q[5:3])); +adffe0 adffe0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[9:6])); +adffe1 adffe1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[13:10])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 + + +# Convert everything to ADFFs. + +design -load orig +dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0 + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 10 adff1/t:$_NOT_ +select -assert-count 2 adffe0/t:$_NOT_ +select -assert-count 12 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 3 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 8 adffe1/t:$_MUX_ +select -assert-count 3 adff0/t:$_DFF_PP0_ +select -assert-count 6 adff1/t:$_DFF_PP0_ +select -assert-count 4 adffe0/t:$_DFF_PP0_ +select -assert-count 8 adffe1/t:$_DFF_PP0_ +select -assert-count 0 adff0/t:$_DLATCH_P_ +select -assert-count 3 adff1/t:$_DLATCH_P_ +select -assert-count 0 adffe0/t:$_DLATCH_P_ +select -assert-count 4 adffe1/t:$_DLATCH_P_ +select -assert-none t:$_DFF_PP0_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0 + +select -assert-count 10 adff0/t:$_NOT_ +select -assert-count 8 adff1/t:$_NOT_ +select -assert-count 12 adffe0/t:$_NOT_ +select -assert-count 10 adffe1/t:$_NOT_ +select -assert-count 3 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 8 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 6 adff0/t:$_DFF_PP0_ +select -assert-count 3 adff1/t:$_DFF_PP0_ +select -assert-count 8 adffe0/t:$_DFF_PP0_ +select -assert-count 4 adffe1/t:$_DFF_PP0_ +select -assert-count 3 adff0/t:$_DLATCH_P_ +select -assert-count 0 adff1/t:$_DLATCH_P_ +select -assert-count 4 adffe0/t:$_DLATCH_P_ +select -assert-count 0 adffe1/t:$_DLATCH_P_ +select -assert-none t:$_DFF_PP0_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0 + +select -assert-count 10 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 12 adffe0/t:$_NOT_ +select -assert-count 2 adffe1/t:$_NOT_ +select -assert-count 3 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 8 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 6 adff0/t:$_DFF_PP1_ +select -assert-count 3 adff1/t:$_DFF_PP1_ +select -assert-count 8 adffe0/t:$_DFF_PP1_ +select -assert-count 4 adffe1/t:$_DFF_PP1_ +select -assert-count 3 adff0/t:$_DLATCH_P_ +select -assert-count 0 adff1/t:$_DLATCH_P_ +select -assert-count 4 adffe0/t:$_DLATCH_P_ +select -assert-count 0 adffe1/t:$_DLATCH_P_ +select -assert-none t:$_DFF_PP1_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0 + +select -assert-count 8 adff0/t:$_NOT_ +select -assert-count 10 adff1/t:$_NOT_ +select -assert-count 10 adffe0/t:$_NOT_ +select -assert-count 12 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 3 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 8 adffe1/t:$_MUX_ +select -assert-count 3 adff0/t:$_DFF_PP1_ +select -assert-count 6 adff1/t:$_DFF_PP1_ +select -assert-count 4 adffe0/t:$_DFF_PP1_ +select -assert-count 8 adffe1/t:$_DFF_PP1_ +select -assert-count 0 adff0/t:$_DLATCH_P_ +select -assert-count 3 adff1/t:$_DLATCH_P_ +select -assert-count 0 adffe0/t:$_DLATCH_P_ +select -assert-count 4 adffe1/t:$_DLATCH_P_ +select -assert-none t:$_DFF_PP1_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ADFFEs. + +design -load orig +dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1 + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 13 adff1/t:$_NOT_ +select -assert-count 3 adffe0/t:$_NOT_ +select -assert-count 18 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 3 adff1/t:$_MUX_ +select -assert-count 0 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 3 adff0/t:$_DFFE_PP0P_ +select -assert-count 6 adff1/t:$_DFFE_PP0P_ +select -assert-count 4 adffe0/t:$_DFFE_PP0P_ +select -assert-count 8 adffe1/t:$_DFFE_PP0P_ +select -assert-count 0 adff0/t:$_DLATCH_P_ +select -assert-count 3 adff1/t:$_DLATCH_P_ +select -assert-count 0 adffe0/t:$_DLATCH_P_ +select -assert-count 4 adffe1/t:$_DLATCH_P_ +select -assert-none t:$_DFFE_PP0P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1 + +select -assert-count 13 adff0/t:$_NOT_ +select -assert-count 8 adff1/t:$_NOT_ +select -assert-count 18 adffe0/t:$_NOT_ +select -assert-count 11 adffe1/t:$_NOT_ +select -assert-count 3 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 0 adffe1/t:$_MUX_ +select -assert-count 6 adff0/t:$_DFFE_PP0P_ +select -assert-count 3 adff1/t:$_DFFE_PP0P_ +select -assert-count 8 adffe0/t:$_DFFE_PP0P_ +select -assert-count 4 adffe1/t:$_DFFE_PP0P_ +select -assert-count 3 adff0/t:$_DLATCH_P_ +select -assert-count 0 adff1/t:$_DLATCH_P_ +select -assert-count 4 adffe0/t:$_DLATCH_P_ +select -assert-count 0 adffe1/t:$_DLATCH_P_ +select -assert-none t:$_DFFE_PP0P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1 + +select -assert-count 10 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 14 adffe0/t:$_NOT_ +select -assert-count 3 adffe1/t:$_NOT_ +select -assert-count 3 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 0 adffe1/t:$_MUX_ +select -assert-count 9 adff0/t:$_DFFE_PP1P_ +select -assert-count 3 adff1/t:$_DFFE_PP1P_ +select -assert-count 12 adffe0/t:$_DFFE_PP1P_ +select -assert-count 4 adffe1/t:$_DFFE_PP1P_ +select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1 + +select -assert-count 8 adff0/t:$_NOT_ +select -assert-count 13 adff1/t:$_NOT_ +select -assert-count 11 adffe0/t:$_NOT_ +select -assert-count 18 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 3 adff1/t:$_MUX_ +select -assert-count 0 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 3 adff0/t:$_DFFE_PP1P_ +select -assert-count 6 adff1/t:$_DFFE_PP1P_ +select -assert-count 4 adffe0/t:$_DFFE_PP1P_ +select -assert-count 8 adffe1/t:$_DFFE_PP1P_ +select -assert-count 0 adff0/t:$_DLATCH_P_ +select -assert-count 3 adff1/t:$_DLATCH_P_ +select -assert-count 0 adffe0/t:$_DLATCH_P_ +select -assert-count 4 adffe1/t:$_DLATCH_P_ +select -assert-none t:$_DFFE_PP1P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 0 + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 2 adffe0/t:$_NOT_ +select -assert-count 2 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 14 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 1 + +select -assert-count 8 adff0/t:$_NOT_ +select -assert-count 8 adff1/t:$_NOT_ +select -assert-count 10 adffe0/t:$_NOT_ +select -assert-count 10 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 14 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 0 + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 3 adffe0/t:$_NOT_ +select -assert-count 3 adffe1/t:$_NOT_ +select -assert-count 14 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 1 + +select -assert-count 8 adff0/t:$_NOT_ +select -assert-count 8 adff1/t:$_NOT_ +select -assert-count 11 adffe0/t:$_NOT_ +select -assert-count 11 adffe1/t:$_NOT_ +select -assert-count 14 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 0 + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 2 adffe0/t:$_NOT_ +select -assert-count 2 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 14 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 1 + +select -assert-count 8 adff0/t:$_NOT_ +select -assert-count 8 adff1/t:$_NOT_ +select -assert-count 10 adffe0/t:$_NOT_ +select -assert-count 10 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 14 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 0 + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 3 adffe0/t:$_NOT_ +select -assert-count 3 adffe1/t:$_NOT_ +select -assert-count 14 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 1 + +select -assert-count 8 adff0/t:$_NOT_ +select -assert-count 8 adff1/t:$_NOT_ +select -assert-count 11 adffe0/t:$_NOT_ +select -assert-count 11 adffe1/t:$_NOT_ +select -assert-count 14 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_adlatch.ys b/tests/techmap/dfflegalize_adlatch.ys new file mode 100644 index 000000000..b242cc809 --- /dev/null +++ b/tests/techmap/dfflegalize_adlatch.ys @@ -0,0 +1,51 @@ +read_verilog -icells <<EOT + +module adlatch0(input E, R, D, output [2:0] Q); +$_DLATCH_PP0_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0])); +$_DLATCH_PN0_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1])); +$_DLATCH_NP0_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2])); +endmodule + +module adlatch1(input E, R, D, output [2:0] Q); +$_DLATCH_PP1_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0])); +$_DLATCH_PN1_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1])); +$_DLATCH_NP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2])); +endmodule + +module top(input C, E, R, D, output [13:0] Q); +adlatch0 adlatch0_(.E(E), .R(R), .D(D), .Q(Q[2:0])); +adlatch1 adlatch1_(.E(E), .R(R), .D(D), .Q(Q[5:3])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ x + +select -assert-count 2 adlatch0/t:$_NOT_ +select -assert-count 8 adlatch1/t:$_NOT_ +select -assert-count 0 adlatch0/t:$_MUX_ +select -assert-count 0 adlatch1/t:$_MUX_ +select -assert-count 6 t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ x + +select -assert-count 2 adlatch0/t:$_NOT_ +select -assert-count 2 adlatch1/t:$_NOT_ +select -assert-count 0 adlatch0/t:$_MUX_ +select -assert-count 0 adlatch1/t:$_MUX_ +select -assert-count 6 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_adlatch_init.ys b/tests/techmap/dfflegalize_adlatch_init.ys new file mode 100644 index 000000000..a55082d1d --- /dev/null +++ b/tests/techmap/dfflegalize_adlatch_init.ys @@ -0,0 +1,99 @@ +read_verilog -icells <<EOT + +module adlatch0(input E, R, D, (* init = 3'b000 *) output [2:0] Q); +$_DLATCH_PP0_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0])); +$_DLATCH_PN0_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1])); +$_DLATCH_NP0_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2])); +endmodule + +module adlatch1(input E, R, D, (* init = 3'b000 *) output [2:0] Q); +$_DLATCH_PP1_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0])); +$_DLATCH_PN1_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1])); +$_DLATCH_NP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2])); +endmodule + +module top(input C, E, R, D, output [13:0] Q); +adlatch0 adlatch0_(.E(E), .R(R), .D(D), .Q(Q[2:0])); +adlatch1 adlatch1_(.E(E), .R(R), .D(D), .Q(Q[5:3])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 0 + +select -assert-count 2 adlatch0/t:$_NOT_ +select -assert-count 10 adlatch1/t:$_NOT_ +select -assert-count 0 adlatch0/t:$_MUX_ +select -assert-count 3 adlatch1/t:$_MUX_ +select -assert-count 3 adlatch0/t:$_DLATCH_PP0_ +select -assert-count 9 adlatch1/t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 1 + +select -assert-count 13 adlatch0/t:$_NOT_ +select -assert-count 8 adlatch1/t:$_NOT_ +select -assert-count 3 adlatch0/t:$_MUX_ +select -assert-count 0 adlatch1/t:$_MUX_ +select -assert-count 9 adlatch0/t:$_DLATCH_PP0_ +select -assert-count 3 adlatch1/t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 0 + +select -assert-count 10 adlatch0/t:$_NOT_ +select -assert-count 2 adlatch1/t:$_NOT_ +select -assert-count 3 adlatch0/t:$_MUX_ +select -assert-count 0 adlatch1/t:$_MUX_ +select -assert-count 9 adlatch0/t:$_DLATCH_PP1_ +select -assert-count 3 adlatch1/t:$_DLATCH_PP1_ +select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 1 + +select -assert-count 8 adlatch0/t:$_NOT_ +select -assert-count 13 adlatch1/t:$_NOT_ +select -assert-count 0 adlatch0/t:$_MUX_ +select -assert-count 3 adlatch1/t:$_MUX_ +select -assert-count 3 adlatch0/t:$_DLATCH_PP1_ +select -assert-count 9 adlatch1/t:$_DLATCH_PP1_ +select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 0 + +select -assert-count 2 adlatch0/t:$_NOT_ +select -assert-count 2 adlatch1/t:$_NOT_ +select -assert-count 0 adlatch0/t:$_MUX_ +select -assert-count 0 adlatch1/t:$_MUX_ +select -assert-count 6 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 1 + +select -assert-count 8 adlatch0/t:$_NOT_ +select -assert-count 8 adlatch1/t:$_NOT_ +select -assert-count 0 adlatch0/t:$_MUX_ +select -assert-count 0 adlatch1/t:$_MUX_ +select -assert-count 6 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_aldff.ys b/tests/techmap/dfflegalize_aldff.ys new file mode 100644 index 000000000..1ee9e3af6 --- /dev/null +++ b/tests/techmap/dfflegalize_aldff.ys @@ -0,0 +1,92 @@ +read_verilog -icells <<EOT + +module aldff(input C, L, AD, D, output [2:0] Q); +$_ALDFF_PP_ ff0 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[0])); +$_ALDFF_PN_ ff1 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[1])); +$_ALDFF_NP_ ff2 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2])); +endmodule + +module aldffe(input C, E, L, AD, D, output [3:0] Q); +$_ALDFFE_PPP_ ff0 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[0])); +$_ALDFFE_PPN_ ff1 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[1])); +$_ALDFFE_PNP_ ff2 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[2])); +$_ALDFFE_NPP_ ff3 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[3])); +endmodule + +module top(input C, E, L, AD, D, output [6:0] Q); +aldff aldff_(.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2:0])); +aldffe aldffe_(.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[6:3])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ x + +select -assert-count 2 aldff/t:$_NOT_ +select -assert-count 2 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ x + +select -assert-count 2 aldff/t:$_NOT_ +select -assert-count 3 aldffe/t:$_NOT_ +select -assert-count 7 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ x + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 3 aldff/t:$_NOT_ +select -assert-count 3 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ x + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 3 aldff/t:$_NOT_ +select -assert-count 4 aldffe/t:$_NOT_ +select -assert-count 7 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_aldff_init.ys b/tests/techmap/dfflegalize_aldff_init.ys new file mode 100644 index 000000000..f4db8dd32 --- /dev/null +++ b/tests/techmap/dfflegalize_aldff_init.ys @@ -0,0 +1,148 @@ +read_verilog -icells <<EOT + +module aldff(input C, L, AD, D, (* init = 3'b000 *) output [2:0] Q); +$_ALDFF_PP_ ff0 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[0])); +$_ALDFF_PN_ ff1 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[1])); +$_ALDFF_NP_ ff2 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2])); +endmodule + +module aldffe(input C, E, L, AD, D, (* init = 4'b0000 *) output [3:0] Q); +$_ALDFFE_PPP_ ff0 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[0])); +$_ALDFFE_PPN_ ff1 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[1])); +$_ALDFFE_PNP_ ff2 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[2])); +$_ALDFFE_NPP_ ff3 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[3])); +endmodule + +module top(input C, E, L, AD, D, output [6:0] Q); +aldff aldff_(.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2:0])); +aldffe aldffe_(.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[6:3])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 0 + +select -assert-count 2 aldff/t:$_NOT_ +select -assert-count 2 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 1 + +select -assert-count 11 aldff/t:$_NOT_ +select -assert-count 14 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 0 + +select -assert-count 2 aldff/t:$_NOT_ +select -assert-count 3 aldffe/t:$_NOT_ +select -assert-count 7 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 1 + +select -assert-count 11 aldff/t:$_NOT_ +select -assert-count 15 aldffe/t:$_NOT_ +select -assert-count 7 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 0 + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 3 aldff/t:$_NOT_ +select -assert-count 3 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 1 + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 12 aldff/t:$_NOT_ +select -assert-count 15 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 0 + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 3 aldff/t:$_NOT_ +select -assert-count 4 aldffe/t:$_NOT_ +select -assert-count 7 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 1 + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 12 aldff/t:$_NOT_ +select -assert-count 16 aldffe/t:$_NOT_ +select -assert-count 7 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dff.ys b/tests/techmap/dfflegalize_dff.ys new file mode 100644 index 000000000..374289678 --- /dev/null +++ b/tests/techmap/dfflegalize_dff.ys @@ -0,0 +1,351 @@ +read_verilog -icells <<EOT + +module dff(input C, D, output [1:0] Q); +$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0])); +$_DFF_N_ ff1 (.C(C), .D(D), .Q(Q[1])); +endmodule + +module dffe(input C, E, D, output [2:0] Q); +$_DFFE_PP_ ff0 (.C(C), .E(E), .D(D), .Q(Q[0])); +$_DFFE_PN_ ff1 (.C(C), .E(E), .D(D), .Q(Q[1])); +$_DFFE_NP_ ff2 (.C(C), .E(E), .D(D), .Q(Q[2])); +endmodule + +module sdff0(input C, R, D, output [2:0] Q); +$_SDFF_PP0_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0])); +$_SDFF_PN0_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1])); +$_SDFF_NP0_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2])); +endmodule + +module sdff1(input C, R, D, output [2:0] Q); +$_SDFF_PP1_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0])); +$_SDFF_PN1_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1])); +$_SDFF_NP1_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2])); +endmodule + +module sdffe0(input C, E, R, D, output [3:0] Q); +$_SDFFE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_SDFFE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_SDFFE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_SDFFE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module sdffe1(input C, E, R, D, output [3:0] Q); +$_SDFFE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_SDFFE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_SDFFE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_SDFFE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module sdffce0(input C, E, R, D, output [3:0] Q); +$_SDFFCE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_SDFFCE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_SDFFCE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_SDFFCE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module sdffce1(input C, E, R, D, output [3:0] Q); +$_SDFFCE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_SDFFCE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_SDFFCE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_SDFFCE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module top(input C, E, R, D, output [26:0] Q); +dff dff_(.C(C), .D(D), .Q(Q[1:0])); +dffe dffe_(.C(C), .E(E), .D(D), .Q(Q[4:2])); +sdff0 sdff0_(.C(C), .R(R), .D(D), .Q(Q[7:5])); +sdff1 sdff1_(.C(C), .R(R), .D(D), .Q(Q[10:8])); +sdffe0 sdffe0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[14:11])); +sdffe1 sdffe1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[18:15])); +sdffce0 sdffce0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[22:19])); +sdffce1 sdffce1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[26:23])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x +equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ x +equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ x + +# Convert everything to DFFs. + +design -load orig +dfflegalize -cell $_DFF_P_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFF_P_ +select -assert-none t:$_DFF_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFEs. + +design -load orig +dfflegalize -cell $_DFFE_PP_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFE_PP_ +select -assert-none t:$_DFFE_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ADFFs. + +design -load orig +dfflegalize -cell $_DFF_PP0_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFF_PP0_ +select -assert-none t:$_DFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ADFFEs. + +design -load orig +dfflegalize -cell $_DFFE_PP0P_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFE_PP0P_ +select -assert-none t:$_DFFE_PP0P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to SDFFs. + +design -load orig +dfflegalize -cell $_SDFF_PP0_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 2 sdff0/t:$_NOT_ +select -assert-count 8 sdff1/t:$_NOT_ +select -assert-count 2 sdffe0/t:$_NOT_ +select -assert-count 10 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 0 sdff0/t:$_MUX_ +select -assert-count 0 sdff1/t:$_MUX_ +select -assert-count 4 sdffe0/t:$_MUX_ +select -assert-count 4 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_SDFF_PP0_ +select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to SDFFEs. + +design -load orig +dfflegalize -cell $_SDFFE_PP0P_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 2 sdff0/t:$_NOT_ +select -assert-count 8 sdff1/t:$_NOT_ +select -assert-count 3 sdffe0/t:$_NOT_ +select -assert-count 11 sdffe1/t:$_NOT_ +select -assert-count 3 sdffce0/t:$_NOT_ +select -assert-count 11 sdffce1/t:$_NOT_ +select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* sdffce1/* %u %n %i +select -assert-count 2 sdffce0/t:$_AND_ +select -assert-count 2 sdffce1/t:$_AND_ +select -assert-count 1 sdffce0/t:$_ORNOT_ +select -assert-count 1 sdffce1/t:$_ORNOT_ +select -assert-count 1 sdffce0/t:$_ANDNOT_ +select -assert-count 1 sdffce1/t:$_ANDNOT_ +select -assert-count 27 t:$_SDFFE_PP0P_ +select -assert-none t:$_SDFFE_PP0P_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i + + +# Convert everything to SDFFCEs. + +design -load orig +dfflegalize -cell $_SDFFCE_PP0P_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 2 sdff0/t:$_NOT_ +select -assert-count 8 sdff1/t:$_NOT_ +select -assert-count 3 sdffe0/t:$_NOT_ +select -assert-count 11 sdffe1/t:$_NOT_ +select -assert-count 3 sdffce0/t:$_NOT_ +select -assert-count 11 sdffce1/t:$_NOT_ +select -assert-count 0 t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffe0/* sdffe1/* %u %n %i +select -assert-count 2 sdffe0/t:$_OR_ +select -assert-count 2 sdffe1/t:$_OR_ +select -assert-count 1 sdffe0/t:$_ORNOT_ +select -assert-count 1 sdffe1/t:$_ORNOT_ +select -assert-count 1 sdffe0/t:$_ANDNOT_ +select -assert-count 1 sdffe1/t:$_ANDNOT_ +select -assert-count 27 t:$_SDFFCE_PP0P_ +select -assert-none t:$_SDFFCE_PP0P_ t:$_NOT_ t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dff_init.ys b/tests/techmap/dfflegalize_dff_init.ys new file mode 100644 index 000000000..a170249c7 --- /dev/null +++ b/tests/techmap/dfflegalize_dff_init.ys @@ -0,0 +1,868 @@ +read_verilog -icells <<EOT + +module dff(input C, D, (* init = 2'b00 *) output [1:0] Q); +$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0])); +$_DFF_N_ ff1 (.C(C), .D(D), .Q(Q[1])); +endmodule + +module dffe(input C, E, D, (* init = 3'b000 *) output [2:0] Q); +$_DFFE_PP_ ff0 (.C(C), .E(E), .D(D), .Q(Q[0])); +$_DFFE_PN_ ff1 (.C(C), .E(E), .D(D), .Q(Q[1])); +$_DFFE_NP_ ff2 (.C(C), .E(E), .D(D), .Q(Q[2])); +endmodule + +module sdff0(input C, R, D, (* init = 3'b000 *) output [2:0] Q); +$_SDFF_PP0_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0])); +$_SDFF_PN0_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1])); +$_SDFF_NP0_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2])); +endmodule + +module sdff1(input C, R, D, (* init = 3'b000 *) output [2:0] Q); +$_SDFF_PP1_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0])); +$_SDFF_PN1_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1])); +$_SDFF_NP1_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2])); +endmodule + +module sdffe0(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q); +$_SDFFE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_SDFFE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_SDFFE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_SDFFE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module sdffe1(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q); +$_SDFFE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_SDFFE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_SDFFE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_SDFFE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module sdffce0(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q); +$_SDFFCE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_SDFFCE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_SDFFCE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_SDFFCE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module sdffce1(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q); +$_SDFFCE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0])); +$_SDFFCE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1])); +$_SDFFCE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2])); +$_SDFFCE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3])); +endmodule + +module top(input C, E, R, D, output [26:0] Q); +dff dff_(.C(C), .D(D), .Q(Q[1:0])); +dffe dffe_(.C(C), .E(E), .D(D), .Q(Q[4:2])); +sdff0 sdff0_(.C(C), .R(R), .D(D), .Q(Q[7:5])); +sdff1 sdff1_(.C(C), .R(R), .D(D), .Q(Q[10:8])); +sdffe0 sdffe0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[14:11])); +sdffe1 sdffe1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[18:15])); +sdffce0 sdffce0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[22:19])); +sdffce1 sdffce1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[26:23])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP1_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP0P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFFE_PP1P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP0P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_SDFFCE_PP1P_ 1 + +# Convert everything to DFFs. + +design -load orig +dfflegalize -cell $_DFF_P_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFF_P_ +select -assert-none t:$_DFF_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_P_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 7 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 9 sdffce0/t:$_NOT_ +select -assert-count 9 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFF_P_ +select -assert-none t:$_DFF_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFEs. + +design -load orig +dfflegalize -cell $_DFFE_PP_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFE_PP_ +select -assert-none t:$_DFFE_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFE_PP_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 8 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 10 sdffce0/t:$_NOT_ +select -assert-count 10 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFE_PP_ +select -assert-none t:$_DFFE_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ADFFs. + +design -load orig +dfflegalize -cell $_DFF_PP0_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFF_PP0_ +select -assert-none t:$_DFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_PP0_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 7 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 9 sdffce0/t:$_NOT_ +select -assert-count 9 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFF_PP0_ +select -assert-none t:$_DFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_PP1_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFF_PP1_ +select -assert-none t:$_DFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_PP1_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 7 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 9 sdffce0/t:$_NOT_ +select -assert-count 9 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFF_PP1_ +select -assert-none t:$_DFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ADFFEs. + +design -load orig +dfflegalize -cell $_DFFE_PP0P_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFE_PP0P_ +select -assert-none t:$_DFFE_PP0P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFE_PP0P_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 8 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 10 sdffce0/t:$_NOT_ +select -assert-count 10 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFE_PP0P_ +select -assert-none t:$_DFFE_PP0P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFE_PP1P_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFE_PP1P_ +select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFE_PP1P_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 8 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 10 sdffce0/t:$_NOT_ +select -assert-count 10 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFE_PP1P_ +select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 7 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 9 sdffce0/t:$_NOT_ +select -assert-count 9 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 8 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 10 sdffce0/t:$_NOT_ +select -assert-count 10 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 7 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 9 sdffce0/t:$_NOT_ +select -assert-count 9 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 8 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 10 sdffce0/t:$_NOT_ +select -assert-count 10 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to SDFFs. + +design -load orig +dfflegalize -cell $_SDFF_PP0_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 2 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 2 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 0 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 4 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_SDFF_PP0_ +select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_SDFF_PP0_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 7 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 8 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 10 sdffe1/t:$_NOT_ +select -assert-count 9 sdffce0/t:$_NOT_ +select -assert-count 9 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 0 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 4 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_SDFF_PP0_ +select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_SDFF_PP1_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 2 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 2 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 0 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 4 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_SDFF_PP1_ +select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_SDFF_PP1_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 7 dffe/t:$_NOT_ +select -assert-count 8 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 10 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 9 sdffce0/t:$_NOT_ +select -assert-count 9 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 0 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 4 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_SDFF_PP1_ +select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to SDFFEs. + +design -load orig +dfflegalize -cell $_SDFFE_PP0P_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 2 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 3 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 3 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 0 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 0 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 0 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i +select -assert-count 2 sdffce0/t:$_AND_ +select -assert-count 1 sdffce0/t:$_ORNOT_ +select -assert-count 1 sdffce0/t:$_ANDNOT_ +select -assert-count 27 t:$_SDFFE_PP0P_ +select -assert-none t:$_SDFFE_PP0P_ t:$_NOT_ t:$_MUX_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_SDFFE_PP0P_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 8 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 8 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 11 sdffe1/t:$_NOT_ +select -assert-count 10 sdffce0/t:$_NOT_ +select -assert-count 11 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 0 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 0 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 0 sdffce1/t:$_MUX_ +select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i +select -assert-count 2 sdffce1/t:$_AND_ +select -assert-count 1 sdffce1/t:$_ORNOT_ +select -assert-count 1 sdffce1/t:$_ANDNOT_ +select -assert-count 27 t:$_SDFFE_PP0P_ +select -assert-none t:$_SDFFE_PP0P_ t:$_NOT_ t:$_MUX_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_SDFFE_PP1P_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 2 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 3 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 3 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 0 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 0 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 0 sdffce1/t:$_MUX_ +select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i +select -assert-count 2 sdffce1/t:$_AND_ +select -assert-count 1 sdffce1/t:$_ORNOT_ +select -assert-count 1 sdffce1/t:$_ANDNOT_ +select -assert-count 27 t:$_SDFFE_PP1P_ +select -assert-none t:$_SDFFE_PP1P_ t:$_NOT_ t:$_MUX_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_SDFFE_PP1P_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 8 dffe/t:$_NOT_ +select -assert-count 8 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 11 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 11 sdffce0/t:$_NOT_ +select -assert-count 10 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 0 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 0 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 0 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i +select -assert-count 2 sdffce0/t:$_AND_ +select -assert-count 1 sdffce0/t:$_ORNOT_ +select -assert-count 1 sdffce0/t:$_ANDNOT_ +select -assert-count 27 t:$_SDFFE_PP1P_ +select -assert-none t:$_SDFFE_PP1P_ t:$_NOT_ t:$_MUX_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i + + +# Convert everything to SDFFCEs. + +design -load orig +dfflegalize -cell $_SDFFCE_PP0P_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 2 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 3 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 3 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 0 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 0 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 0 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 0 t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffe0/* %n %i +select -assert-count 2 sdffe0/t:$_OR_ +select -assert-count 1 sdffe0/t:$_ORNOT_ +select -assert-count 1 sdffe0/t:$_ANDNOT_ +select -assert-count 27 t:$_SDFFCE_PP0P_ +select -assert-none t:$_SDFFCE_PP0P_ t:$_NOT_ t:$_MUX_ t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_SDFFCE_PP0P_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 8 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 8 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 11 sdffe1/t:$_NOT_ +select -assert-count 10 sdffce0/t:$_NOT_ +select -assert-count 11 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 0 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 0 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 0 sdffce1/t:$_MUX_ +select -assert-count 0 t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffe1/* %n %i +select -assert-count 2 sdffe1/t:$_OR_ +select -assert-count 1 sdffe1/t:$_ORNOT_ +select -assert-count 1 sdffe1/t:$_ANDNOT_ +select -assert-count 27 t:$_SDFFCE_PP0P_ +select -assert-none t:$_SDFFCE_PP0P_ t:$_NOT_ t:$_MUX_ t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_SDFFCE_PP1P_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 2 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 3 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 3 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 0 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 0 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 0 sdffce1/t:$_MUX_ +select -assert-count 0 t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffe1/* %n %i +select -assert-count 2 sdffe1/t:$_OR_ +select -assert-count 1 sdffe1/t:$_ORNOT_ +select -assert-count 1 sdffe1/t:$_ANDNOT_ +select -assert-count 27 t:$_SDFFCE_PP1P_ +select -assert-none t:$_SDFFCE_PP1P_ t:$_NOT_ t:$_MUX_ t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_SDFFCE_PP1P_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 8 dffe/t:$_NOT_ +select -assert-count 8 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 11 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 11 sdffce0/t:$_NOT_ +select -assert-count 10 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 0 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 0 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 0 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 0 t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffe0/* %n %i +select -assert-count 2 sdffe0/t:$_OR_ +select -assert-count 1 sdffe0/t:$_ORNOT_ +select -assert-count 1 sdffe0/t:$_ANDNOT_ +select -assert-count 27 t:$_SDFFCE_PP1P_ +select -assert-none t:$_SDFFCE_PP1P_ t:$_NOT_ t:$_MUX_ t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dffsr.ys b/tests/techmap/dfflegalize_dffsr.ys new file mode 100644 index 000000000..49a7237a2 --- /dev/null +++ b/tests/techmap/dfflegalize_dffsr.ys @@ -0,0 +1,88 @@ +read_verilog -icells <<EOT + +module dffsr(input C, R, S, D, output [3:0] Q); +$_DFFSR_PPP_ ff0 (.C(C), .R(R), .S(S), .D(D), .Q(Q[0])); +$_DFFSR_PPN_ ff1 (.C(C), .R(R), .S(S), .D(D), .Q(Q[1])); +$_DFFSR_PNP_ ff2 (.C(C), .R(R), .S(S), .D(D), .Q(Q[2])); +$_DFFSR_NPP_ ff3 (.C(C), .R(R), .S(S), .D(D), .Q(Q[3])); +endmodule + +module dffsre(input C, R, S, E, D, output [4:0] Q); +$_DFFSRE_PPPP_ ff0 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[0])); +$_DFFSRE_PPPN_ ff1 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[1])); +$_DFFSRE_PPNP_ ff2 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[2])); +$_DFFSRE_PNPP_ ff3 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[3])); +$_DFFSRE_NPPP_ ff4 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[4])); +endmodule + +module top(input C, E, R, S, D, output [8:0] Q); +dffsr dffsr_(.C(C), .R(R), .S(S), .D(D), .Q(Q[3:0])); +dffsre dffsre_(.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[8:4])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x + + +# Convert everything to ADFFs. + +design -load orig +dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x + +select -assert-count 14 dffsr/t:$_NOT_ +select -assert-count 16 dffsre/t:$_NOT_ +select -assert-count 4 dffsr/t:$_MUX_ +select -assert-count 10 dffsre/t:$_MUX_ +select -assert-count 8 dffsr/t:$_DFF_PP0_ +select -assert-count 10 dffsre/t:$_DFF_PP0_ +select -assert-count 4 dffsr/t:$_SR_PP_ +select -assert-count 5 dffsre/t:$_SR_PP_ +select -assert-none t:$_DFF_PP0_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ADFFEs. + +design -load orig +dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x + +select -assert-count 14 dffsr/t:$_NOT_ +select -assert-count 18 dffsre/t:$_NOT_ +select -assert-count 4 dffsr/t:$_MUX_ +select -assert-count 5 dffsre/t:$_MUX_ +select -assert-count 8 dffsr/t:$_DFFE_PP0P_ +select -assert-count 10 dffsre/t:$_DFFE_PP0P_ +select -assert-count 4 dffsr/t:$_SR_PP_ +select -assert-count 5 dffsre/t:$_SR_PP_ +select -assert-none t:$_DFFE_PP0P_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ x + +select -assert-count 3 dffsr/t:$_NOT_ +select -assert-count 3 dffsre/t:$_NOT_ +select -assert-count 0 dffsr/t:$_MUX_ +select -assert-count 5 dffsre/t:$_MUX_ +select -assert-count 4 dffsr/t:$_DFFSR_PPP_ +select -assert-count 5 dffsre/t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ x + +select -assert-count 3 dffsr/t:$_NOT_ +select -assert-count 4 dffsre/t:$_NOT_ +select -assert-count 4 dffsr/t:$_DFFSRE_PPPP_ +select -assert-count 5 dffsre/t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dffsr_init.ys b/tests/techmap/dfflegalize_dffsr_init.ys new file mode 100644 index 000000000..ce5a32f76 --- /dev/null +++ b/tests/techmap/dfflegalize_dffsr_init.ys @@ -0,0 +1,379 @@ +read_verilog -icells <<EOT + +module dffsr0(input C, R, S, D, (* init = 4'h0 *) output [3:0] Q); +$_DFFSR_PPP_ ff0 (.C(C), .R(R), .S(S), .D(D), .Q(Q[0])); +$_DFFSR_PPN_ ff1 (.C(C), .R(R), .S(S), .D(D), .Q(Q[1])); +$_DFFSR_PNP_ ff2 (.C(C), .R(R), .S(S), .D(D), .Q(Q[2])); +$_DFFSR_NPP_ ff3 (.C(C), .R(R), .S(S), .D(D), .Q(Q[3])); +endmodule + +module dffsr1(input C, R, S, D, (* init = 4'hf *) output [3:0] Q); +$_DFFSR_PPP_ ff0 (.C(C), .R(R), .S(S), .D(D), .Q(Q[0])); +$_DFFSR_PPN_ ff1 (.C(C), .R(R), .S(S), .D(D), .Q(Q[1])); +$_DFFSR_PNP_ ff2 (.C(C), .R(R), .S(S), .D(D), .Q(Q[2])); +$_DFFSR_NPP_ ff3 (.C(C), .R(R), .S(S), .D(D), .Q(Q[3])); +endmodule + +module dffsre0(input C, R, S, E, D, (* init = 5'h0 *) output [4:0] Q); +$_DFFSRE_PPPP_ ff0 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[0])); +$_DFFSRE_PPPN_ ff1 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[1])); +$_DFFSRE_PPNP_ ff2 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[2])); +$_DFFSRE_PNPP_ ff3 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[3])); +$_DFFSRE_NPPP_ ff4 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[4])); +endmodule + +module dffsre1(input C, R, S, E, D, (* init = 5'h1f *) output [4:0] Q); +$_DFFSRE_PPPP_ ff0 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[0])); +$_DFFSRE_PPPN_ ff1 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[1])); +$_DFFSRE_PPNP_ ff2 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[2])); +$_DFFSRE_PNPP_ ff3 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[3])); +$_DFFSRE_NPPP_ ff4 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[4])); +endmodule + +module top(input C, E, R, S, D, output [17:0] Q); +dffsr0 dffsr0_(.C(C), .R(R), .S(S), .D(D), .Q(Q[3:0])); +dffsr1 dffsr1_(.C(C), .R(R), .S(S), .D(D), .Q(Q[7:4])); +dffsre0 dffsre0_(.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[12:8])); +dffsre1 dffsre1_(.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[17:13])); +endmodule + +EOT + +design -save orig +flatten +#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 + + +# Convert everything to ADFFs. + +design -load orig +dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0 + +select -assert-count 14 dffsr0/t:$_NOT_ +select -assert-count 18 dffsr1/t:$_NOT_ +select -assert-count 16 dffsre0/t:$_NOT_ +select -assert-count 21 dffsre1/t:$_NOT_ +select -assert-count 4 dffsr0/t:$_MUX_ +select -assert-count 4 dffsr1/t:$_MUX_ +select -assert-count 10 dffsre0/t:$_MUX_ +select -assert-count 10 dffsre1/t:$_MUX_ +select -assert-count 8 dffsr0/t:$_DFF_PP0_ +select -assert-count 8 dffsr1/t:$_DFF_PP0_ +select -assert-count 10 dffsre0/t:$_DFF_PP0_ +select -assert-count 10 dffsre1/t:$_DFF_PP0_ +select -assert-count 4 dffsr0/t:$_SR_PP_ +select -assert-count 4 dffsr1/t:$_SR_PP_ +select -assert-count 5 dffsre0/t:$_SR_PP_ +select -assert-count 5 dffsre1/t:$_SR_PP_ +select -assert-count 1 dffsr1/t:$_AND_ +select -assert-count 2 dffsr1/t:$_ANDNOT_ +select -assert-count 1 dffsr1/t:$_OR_ +select -assert-count 1 dffsre1/t:$_AND_ +select -assert-count 3 dffsre1/t:$_ANDNOT_ +select -assert-count 1 dffsre1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i +select -assert-none t:$_DFF_PP0_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0 + +select -assert-count 18 dffsr0/t:$_NOT_ +select -assert-count 14 dffsr1/t:$_NOT_ +select -assert-count 21 dffsre0/t:$_NOT_ +select -assert-count 16 dffsre1/t:$_NOT_ +select -assert-count 4 dffsr0/t:$_MUX_ +select -assert-count 4 dffsr1/t:$_MUX_ +select -assert-count 10 dffsre0/t:$_MUX_ +select -assert-count 10 dffsre1/t:$_MUX_ +select -assert-count 8 dffsr0/t:$_DFF_PP0_ +select -assert-count 8 dffsr1/t:$_DFF_PP0_ +select -assert-count 10 dffsre0/t:$_DFF_PP0_ +select -assert-count 10 dffsre1/t:$_DFF_PP0_ +select -assert-count 4 dffsr0/t:$_SR_PP_ +select -assert-count 4 dffsr1/t:$_SR_PP_ +select -assert-count 5 dffsre0/t:$_SR_PP_ +select -assert-count 5 dffsre1/t:$_SR_PP_ +select -assert-count 1 dffsr0/t:$_AND_ +select -assert-count 2 dffsr0/t:$_ANDNOT_ +select -assert-count 1 dffsr0/t:$_OR_ +select -assert-count 1 dffsre0/t:$_AND_ +select -assert-count 3 dffsre0/t:$_ANDNOT_ +select -assert-count 1 dffsre0/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i +select -assert-none t:$_DFF_PP0_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0 + +select -assert-count 18 dffsr0/t:$_NOT_ +select -assert-count 14 dffsr1/t:$_NOT_ +select -assert-count 21 dffsre0/t:$_NOT_ +select -assert-count 16 dffsre1/t:$_NOT_ +select -assert-count 4 dffsr0/t:$_MUX_ +select -assert-count 4 dffsr1/t:$_MUX_ +select -assert-count 10 dffsre0/t:$_MUX_ +select -assert-count 10 dffsre1/t:$_MUX_ +select -assert-count 8 dffsr0/t:$_DFF_PP1_ +select -assert-count 8 dffsr1/t:$_DFF_PP1_ +select -assert-count 10 dffsre0/t:$_DFF_PP1_ +select -assert-count 10 dffsre1/t:$_DFF_PP1_ +select -assert-count 4 dffsr0/t:$_SR_PP_ +select -assert-count 4 dffsr1/t:$_SR_PP_ +select -assert-count 5 dffsre0/t:$_SR_PP_ +select -assert-count 5 dffsre1/t:$_SR_PP_ +select -assert-count 1 dffsr0/t:$_AND_ +select -assert-count 2 dffsr0/t:$_ANDNOT_ +select -assert-count 1 dffsr0/t:$_OR_ +select -assert-count 1 dffsre0/t:$_AND_ +select -assert-count 3 dffsre0/t:$_ANDNOT_ +select -assert-count 1 dffsre0/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i +select -assert-none t:$_DFF_PP1_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0 + +select -assert-count 14 dffsr0/t:$_NOT_ +select -assert-count 18 dffsr1/t:$_NOT_ +select -assert-count 16 dffsre0/t:$_NOT_ +select -assert-count 21 dffsre1/t:$_NOT_ +select -assert-count 4 dffsr0/t:$_MUX_ +select -assert-count 4 dffsr1/t:$_MUX_ +select -assert-count 10 dffsre0/t:$_MUX_ +select -assert-count 10 dffsre1/t:$_MUX_ +select -assert-count 8 dffsr0/t:$_DFF_PP1_ +select -assert-count 8 dffsr1/t:$_DFF_PP1_ +select -assert-count 10 dffsre0/t:$_DFF_PP1_ +select -assert-count 10 dffsre1/t:$_DFF_PP1_ +select -assert-count 4 dffsr0/t:$_SR_PP_ +select -assert-count 4 dffsr1/t:$_SR_PP_ +select -assert-count 5 dffsre0/t:$_SR_PP_ +select -assert-count 5 dffsre1/t:$_SR_PP_ +select -assert-count 1 dffsr1/t:$_AND_ +select -assert-count 2 dffsr1/t:$_ANDNOT_ +select -assert-count 1 dffsr1/t:$_OR_ +select -assert-count 1 dffsre1/t:$_AND_ +select -assert-count 3 dffsre1/t:$_ANDNOT_ +select -assert-count 1 dffsre1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i +select -assert-none t:$_DFF_PP1_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + + +# Convert everything to ADFFEs. + +design -load orig +dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 1 + +select -assert-count 18 dffsr0/t:$_NOT_ +select -assert-count 14 dffsr1/t:$_NOT_ +select -assert-count 23 dffsre0/t:$_NOT_ +select -assert-count 18 dffsre1/t:$_NOT_ +select -assert-count 4 dffsr0/t:$_MUX_ +select -assert-count 4 dffsr1/t:$_MUX_ +select -assert-count 5 dffsre0/t:$_MUX_ +select -assert-count 5 dffsre1/t:$_MUX_ +select -assert-count 8 dffsr0/t:$_DFFE_PP0P_ +select -assert-count 8 dffsr1/t:$_DFFE_PP0P_ +select -assert-count 10 dffsre0/t:$_DFFE_PP0P_ +select -assert-count 10 dffsre1/t:$_DFFE_PP0P_ +select -assert-count 4 dffsr0/t:$_SR_PP_ +select -assert-count 4 dffsr1/t:$_SR_PP_ +select -assert-count 5 dffsre0/t:$_SR_PP_ +select -assert-count 5 dffsre1/t:$_SR_PP_ +select -assert-count 1 dffsr0/t:$_AND_ +select -assert-count 2 dffsr0/t:$_ANDNOT_ +select -assert-count 1 dffsr0/t:$_OR_ +select -assert-count 1 dffsre0/t:$_AND_ +select -assert-count 3 dffsre0/t:$_ANDNOT_ +select -assert-count 1 dffsre0/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i +select -assert-none t:$_DFFE_PP0P_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 1 + +select -assert-count 14 dffsr0/t:$_NOT_ +select -assert-count 18 dffsr1/t:$_NOT_ +select -assert-count 18 dffsre0/t:$_NOT_ +select -assert-count 23 dffsre1/t:$_NOT_ +select -assert-count 4 dffsr0/t:$_MUX_ +select -assert-count 4 dffsr1/t:$_MUX_ +select -assert-count 5 dffsre0/t:$_MUX_ +select -assert-count 5 dffsre1/t:$_MUX_ +select -assert-count 8 dffsr0/t:$_DFFE_PP0P_ +select -assert-count 8 dffsr1/t:$_DFFE_PP0P_ +select -assert-count 10 dffsre0/t:$_DFFE_PP0P_ +select -assert-count 10 dffsre1/t:$_DFFE_PP0P_ +select -assert-count 4 dffsr0/t:$_SR_PP_ +select -assert-count 4 dffsr1/t:$_SR_PP_ +select -assert-count 5 dffsre0/t:$_SR_PP_ +select -assert-count 5 dffsre1/t:$_SR_PP_ +select -assert-count 1 dffsr1/t:$_AND_ +select -assert-count 2 dffsr1/t:$_ANDNOT_ +select -assert-count 1 dffsr1/t:$_OR_ +select -assert-count 1 dffsre1/t:$_AND_ +select -assert-count 3 dffsre1/t:$_ANDNOT_ +select -assert-count 1 dffsre1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i +select -assert-none t:$_DFFE_PP0P_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 1 + +select -assert-count 14 dffsr0/t:$_NOT_ +select -assert-count 18 dffsr1/t:$_NOT_ +select -assert-count 18 dffsre0/t:$_NOT_ +select -assert-count 23 dffsre1/t:$_NOT_ +select -assert-count 4 dffsr0/t:$_MUX_ +select -assert-count 4 dffsr1/t:$_MUX_ +select -assert-count 5 dffsre0/t:$_MUX_ +select -assert-count 5 dffsre1/t:$_MUX_ +select -assert-count 8 dffsr0/t:$_DFFE_PP1P_ +select -assert-count 8 dffsr1/t:$_DFFE_PP1P_ +select -assert-count 10 dffsre0/t:$_DFFE_PP1P_ +select -assert-count 10 dffsre1/t:$_DFFE_PP1P_ +select -assert-count 4 dffsr0/t:$_SR_PP_ +select -assert-count 4 dffsr1/t:$_SR_PP_ +select -assert-count 5 dffsre0/t:$_SR_PP_ +select -assert-count 5 dffsre1/t:$_SR_PP_ +select -assert-count 1 dffsr1/t:$_AND_ +select -assert-count 2 dffsr1/t:$_ANDNOT_ +select -assert-count 1 dffsr1/t:$_OR_ +select -assert-count 1 dffsre1/t:$_AND_ +select -assert-count 3 dffsre1/t:$_ANDNOT_ +select -assert-count 1 dffsre1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i +select -assert-none t:$_DFFE_PP1P_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 1 + +select -assert-count 18 dffsr0/t:$_NOT_ +select -assert-count 14 dffsr1/t:$_NOT_ +select -assert-count 23 dffsre0/t:$_NOT_ +select -assert-count 18 dffsre1/t:$_NOT_ +select -assert-count 4 dffsr0/t:$_MUX_ +select -assert-count 4 dffsr1/t:$_MUX_ +select -assert-count 5 dffsre0/t:$_MUX_ +select -assert-count 5 dffsre1/t:$_MUX_ +select -assert-count 8 dffsr0/t:$_DFFE_PP1P_ +select -assert-count 8 dffsr1/t:$_DFFE_PP1P_ +select -assert-count 10 dffsre0/t:$_DFFE_PP1P_ +select -assert-count 10 dffsre1/t:$_DFFE_PP1P_ +select -assert-count 4 dffsr0/t:$_SR_PP_ +select -assert-count 4 dffsr1/t:$_SR_PP_ +select -assert-count 5 dffsre0/t:$_SR_PP_ +select -assert-count 5 dffsre1/t:$_SR_PP_ +select -assert-count 1 dffsr0/t:$_AND_ +select -assert-count 2 dffsr0/t:$_ANDNOT_ +select -assert-count 1 dffsr0/t:$_OR_ +select -assert-count 1 dffsre0/t:$_AND_ +select -assert-count 3 dffsre0/t:$_ANDNOT_ +select -assert-count 1 dffsre0/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i +select -assert-none t:$_DFFE_PP1P_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 0 + +select -assert-count 3 dffsr0/t:$_NOT_ +select -assert-count 11 dffsr1/t:$_NOT_ +select -assert-count 3 dffsre0/t:$_NOT_ +select -assert-count 13 dffsre1/t:$_NOT_ +select -assert-count 0 dffsr0/t:$_MUX_ +select -assert-count 0 dffsr1/t:$_MUX_ +select -assert-count 5 dffsre0/t:$_MUX_ +select -assert-count 5 dffsre1/t:$_MUX_ +select -assert-count 4 dffsr0/t:$_DFFSR_PPP_ +select -assert-count 4 dffsr1/t:$_DFFSR_PPP_ +select -assert-count 5 dffsre0/t:$_DFFSR_PPP_ +select -assert-count 5 dffsre1/t:$_DFFSR_PPP_ +select -assert-count 1 dffsr1/t:$_AND_ +select -assert-count 2 dffsr1/t:$_ANDNOT_ +select -assert-count 1 dffsr1/t:$_OR_ +select -assert-count 1 dffsre1/t:$_AND_ +select -assert-count 3 dffsre1/t:$_ANDNOT_ +select -assert-count 1 dffsre1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 1 + +select -assert-count 11 dffsr0/t:$_NOT_ +select -assert-count 3 dffsr1/t:$_NOT_ +select -assert-count 13 dffsre0/t:$_NOT_ +select -assert-count 3 dffsre1/t:$_NOT_ +select -assert-count 0 dffsr0/t:$_MUX_ +select -assert-count 0 dffsr1j/t:$_MUX_ +select -assert-count 5 dffsre0/t:$_MUX_ +select -assert-count 5 dffsre1/t:$_MUX_ +select -assert-count 4 dffsr0/t:$_DFFSR_PPP_ +select -assert-count 4 dffsr1/t:$_DFFSR_PPP_ +select -assert-count 5 dffsre0/t:$_DFFSR_PPP_ +select -assert-count 5 dffsre1/t:$_DFFSR_PPP_ +select -assert-count 1 dffsr0/t:$_AND_ +select -assert-count 2 dffsr0/t:$_ANDNOT_ +select -assert-count 1 dffsr0/t:$_OR_ +select -assert-count 1 dffsre0/t:$_AND_ +select -assert-count 3 dffsre0/t:$_ANDNOT_ +select -assert-count 1 dffsre0/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 0 + +select -assert-count 3 dffsr0/t:$_NOT_ +select -assert-count 11 dffsr1/t:$_NOT_ +select -assert-count 4 dffsre0/t:$_NOT_ +select -assert-count 14 dffsre1/t:$_NOT_ +select -assert-count 4 dffsr0/t:$_DFFSRE_PPPP_ +select -assert-count 4 dffsr1/t:$_DFFSRE_PPPP_ +select -assert-count 5 dffsre0/t:$_DFFSRE_PPPP_ +select -assert-count 5 dffsre1/t:$_DFFSRE_PPPP_ +select -assert-count 1 dffsr1/t:$_AND_ +select -assert-count 2 dffsr1/t:$_ANDNOT_ +select -assert-count 1 dffsr1/t:$_OR_ +select -assert-count 1 dffsre1/t:$_AND_ +select -assert-count 3 dffsre1/t:$_ANDNOT_ +select -assert-count 1 dffsre1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 1 + +select -assert-count 11 dffsr0/t:$_NOT_ +select -assert-count 3 dffsr1/t:$_NOT_ +select -assert-count 14 dffsre0/t:$_NOT_ +select -assert-count 4 dffsre1/t:$_NOT_ +select -assert-count 4 dffsr0/t:$_DFFSRE_PPPP_ +select -assert-count 4 dffsr1/t:$_DFFSRE_PPPP_ +select -assert-count 5 dffsre0/t:$_DFFSRE_PPPP_ +select -assert-count 5 dffsre1/t:$_DFFSRE_PPPP_ +select -assert-count 1 dffsr0/t:$_AND_ +select -assert-count 2 dffsr0/t:$_ANDNOT_ +select -assert-count 1 dffsr0/t:$_OR_ +select -assert-count 1 dffsre0/t:$_AND_ +select -assert-count 3 dffsre0/t:$_ANDNOT_ +select -assert-count 1 dffsre0/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dlatch.ys b/tests/techmap/dfflegalize_dlatch.ys new file mode 100644 index 000000000..11683bc1a --- /dev/null +++ b/tests/techmap/dfflegalize_dlatch.ys @@ -0,0 +1,64 @@ +read_verilog -icells <<EOT + +module dlatch(input E, D, output [1:0] Q); +$_DLATCH_P_ ff0 (.E(E), .D(D), .Q(Q[0])); +$_DLATCH_N_ ff1 (.E(E), .D(D), .Q(Q[1])); +endmodule + +EOT + +design -save orig +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x + +# Convert everything to DFFs. + +design -load orig +dfflegalize -cell $_DLATCH_P_ x + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_P_ +select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ x + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ x + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ x + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ x + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dlatch_const.ys b/tests/techmap/dfflegalize_dlatch_const.ys new file mode 100644 index 000000000..159692249 --- /dev/null +++ b/tests/techmap/dfflegalize_dlatch_const.ys @@ -0,0 +1,53 @@ +read_verilog -icells <<EOT + +module dlatch(input E, D, (* init = 8'hf0 *) output [7:0] Q); +$_DLATCH_P_ ff0 (.E(E), .D(1'b0), .Q(Q[0])); +$_DLATCH_N_ ff1 (.E(E), .D(1'b0), .Q(Q[1])); +$_DLATCH_P_ ff2 (.E(E), .D(1'b1), .Q(Q[2])); +$_DLATCH_N_ ff3 (.E(E), .D(1'b1), .Q(Q[3])); +$_DLATCH_P_ ff4 (.E(E), .D(1'b0), .Q(Q[4])); +$_DLATCH_N_ ff5 (.E(E), .D(1'b0), .Q(Q[5])); +$_DLATCH_P_ ff6 (.E(E), .D(1'b1), .Q(Q[6])); +$_DLATCH_N_ ff7 (.E(E), .D(1'b1), .Q(Q[7])); +endmodule + +EOT + +design -save orig +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ 01 +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP?_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 + +# Convert everything to ADFFs. + +design -load orig +dfflegalize -cell $_DFF_PP0_ 01 + +select -assert-count 8 t:$_NOT_ +select -assert-count 8 t:$_DFF_PP0_ +select -assert-none t:$_DFF_PP0_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFF_PP?_ 0 + +select -assert-count 8 t:$_NOT_ +select -assert-count 4 t:$_DFF_PP0_ +select -assert-count 4 t:$_DFF_PP1_ +select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_NOT_ %% %n t:* %i + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 0 + +select -assert-count 8 t:$_NOT_ +select -assert-count 8 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 1 + +select -assert-count 8 t:$_NOT_ +select -assert-count 8 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dlatch_init.ys b/tests/techmap/dfflegalize_dlatch_init.ys new file mode 100644 index 000000000..9324c6691 --- /dev/null +++ b/tests/techmap/dfflegalize_dlatch_init.ys @@ -0,0 +1,120 @@ +read_verilog -icells <<EOT + +module dlatch(input E, D, (* init = 2'h0 *) output [1:0] Q); +$_DLATCH_P_ ff0 (.E(E), .D(D), .Q(Q[0])); +$_DLATCH_N_ ff1 (.E(E), .D(D), .Q(Q[1])); +endmodule + +EOT + +design -save orig +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 + +# Convert everything to DFFs. + +design -load orig +dfflegalize -cell $_DLATCH_P_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_P_ +select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_P_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_P_ +select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_PP1_ +select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_DLATCH_PP1_ +select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dlatchsr.ys b/tests/techmap/dfflegalize_dlatchsr.ys new file mode 100644 index 000000000..53d910723 --- /dev/null +++ b/tests/techmap/dfflegalize_dlatchsr.ys @@ -0,0 +1,37 @@ +read_verilog -icells <<EOT + +module dlatchsr(input E, R, S, D, output [3:0] Q); +$_DLATCHSR_PPP_ ff0 (.E(E), .R(R), .S(S), .D(D), .Q(Q[0])); +$_DLATCHSR_PPN_ ff1 (.E(E), .R(R), .S(S), .D(D), .Q(Q[1])); +$_DLATCHSR_PNP_ ff2 (.E(E), .R(R), .S(S), .D(D), .Q(Q[2])); +$_DLATCHSR_NPP_ ff3 (.E(E), .R(R), .S(S), .D(D), .Q(Q[3])); +endmodule + +EOT + +design -save orig +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x + +select -assert-count 14 t:$_NOT_ +select -assert-count 4 t:$_MUX_ +select -assert-count 8 t:$_DLATCH_PP0_ +select -assert-count 4 t:$_SR_PP_ +select -assert-none t:$_DLATCH_PP0_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ x + +select -assert-count 3 t:$_NOT_ +select -assert-count 0 t:$_MUX_ +select -assert-count 4 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dlatchsr_init.ys b/tests/techmap/dfflegalize_dlatchsr_init.ys new file mode 100644 index 000000000..b38a9eb3b --- /dev/null +++ b/tests/techmap/dfflegalize_dlatchsr_init.ys @@ -0,0 +1,127 @@ +read_verilog -icells <<EOT + +module dlatchsr0(input E, R, S, D, (* init = 4'h0 *) output [3:0] Q); +$_DLATCHSR_PPP_ ff0 (.E(E), .R(R), .S(S), .D(D), .Q(Q[0])); +$_DLATCHSR_PPN_ ff1 (.E(E), .R(R), .S(S), .D(D), .Q(Q[1])); +$_DLATCHSR_PNP_ ff2 (.E(E), .R(R), .S(S), .D(D), .Q(Q[2])); +$_DLATCHSR_NPP_ ff3 (.E(E), .R(R), .S(S), .D(D), .Q(Q[3])); +endmodule + +module dlatchsr1(input E, R, S, D, (* init = 4'hf *) output [3:0] Q); +$_DLATCHSR_PPP_ ff0 (.E(E), .R(R), .S(S), .D(D), .Q(Q[0])); +$_DLATCHSR_PPN_ ff1 (.E(E), .R(R), .S(S), .D(D), .Q(Q[1])); +$_DLATCHSR_PNP_ ff2 (.E(E), .R(R), .S(S), .D(D), .Q(Q[2])); +$_DLATCHSR_NPP_ ff3 (.E(E), .R(R), .S(S), .D(D), .Q(Q[3])); +endmodule + +module top(input C, E, R, S, D, output [17:0] Q); +dlatchsr0 dlatchsr0_(.E(E), .R(R), .S(S), .D(D), .Q(Q[3:0])); +dlatchsr1 dlatchsr1_(.E(E), .R(R), .S(S), .D(D), .Q(Q[7:4])); +endmodule + +EOT + +design -save orig +flatten +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 0 + +select -assert-count 14 dlatchsr0/t:$_NOT_ +select -assert-count 18 dlatchsr1/t:$_NOT_ +select -assert-count 4 dlatchsr0/t:$_MUX_ +select -assert-count 4 dlatchsr1/t:$_MUX_ +select -assert-count 12 dlatchsr0/t:$_DLATCH_PP0_ +select -assert-count 12 dlatchsr1/t:$_DLATCH_PP0_ +select -assert-count 1 dlatchsr1/t:$_AND_ +select -assert-count 2 dlatchsr1/t:$_ANDNOT_ +select -assert-count 1 dlatchsr1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr1/* %n %i +select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 1 + +select -assert-count 14 dlatchsr0/t:$_NOT_ +select -assert-count 18 dlatchsr1/t:$_NOT_ +select -assert-count 4 dlatchsr0/t:$_MUX_ +select -assert-count 4 dlatchsr1/t:$_MUX_ +select -assert-count 12 dlatchsr0/t:$_DLATCH_PP0_ +select -assert-count 12 dlatchsr1/t:$_DLATCH_PP0_ +select -assert-count 1 dlatchsr1/t:$_AND_ +select -assert-count 2 dlatchsr1/t:$_ANDNOT_ +select -assert-count 1 dlatchsr1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr1/* %n %i +select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 0 + +select -assert-count 18 dlatchsr0/t:$_NOT_ +select -assert-count 22 dlatchsr1/t:$_NOT_ +select -assert-count 4 dlatchsr0/t:$_MUX_ +select -assert-count 4 dlatchsr1/t:$_MUX_ +select -assert-count 12 dlatchsr0/t:$_DLATCH_PP1_ +select -assert-count 12 dlatchsr1/t:$_DLATCH_PP1_ +select -assert-count 1 dlatchsr1/t:$_AND_ +select -assert-count 2 dlatchsr1/t:$_ANDNOT_ +select -assert-count 1 dlatchsr1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr1/* %n %i +select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 1 + +select -assert-count 18 dlatchsr0/t:$_NOT_ +select -assert-count 22 dlatchsr1/t:$_NOT_ +select -assert-count 4 dlatchsr0/t:$_MUX_ +select -assert-count 4 dlatchsr1/t:$_MUX_ +select -assert-count 12 dlatchsr0/t:$_DLATCH_PP1_ +select -assert-count 12 dlatchsr1/t:$_DLATCH_PP1_ +select -assert-count 1 dlatchsr1/t:$_AND_ +select -assert-count 2 dlatchsr1/t:$_ANDNOT_ +select -assert-count 1 dlatchsr1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr1/* %n %i +select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 0 + +select -assert-count 3 dlatchsr0/t:$_NOT_ +select -assert-count 11 dlatchsr1/t:$_NOT_ +select -assert-count 0 dlatchsr0/t:$_MUX_ +select -assert-count 0 dlatchsr1/t:$_MUX_ +select -assert-count 4 dlatchsr0/t:$_DLATCHSR_PPP_ +select -assert-count 4 dlatchsr1/t:$_DLATCHSR_PPP_ +select -assert-count 1 dlatchsr1/t:$_AND_ +select -assert-count 2 dlatchsr1/t:$_ANDNOT_ +select -assert-count 1 dlatchsr1/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr1/* %n %i +select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 1 + +select -assert-count 11 dlatchsr0/t:$_NOT_ +select -assert-count 3 dlatchsr1/t:$_NOT_ +select -assert-count 0 dlatchsr0/t:$_MUX_ +select -assert-count 0 dlatchsr1j/t:$_MUX_ +select -assert-count 4 dlatchsr0/t:$_DLATCHSR_PPP_ +select -assert-count 4 dlatchsr1/t:$_DLATCHSR_PPP_ +select -assert-count 1 dlatchsr0/t:$_AND_ +select -assert-count 2 dlatchsr0/t:$_ANDNOT_ +select -assert-count 1 dlatchsr0/t:$_OR_ +select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr0/* %n %i +select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_inv.ys b/tests/techmap/dfflegalize_inv.ys new file mode 100644 index 000000000..a74d74161 --- /dev/null +++ b/tests/techmap/dfflegalize_inv.ys @@ -0,0 +1,191 @@ +# Base test: make sure inverters are applied correctly. + +read_verilog -icells <<EOT + +module top(input C, E, R, S, D, L, AD, output [71:0] Q); + +$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0])); +$_DFF_N_ ff1 (.C(C), .D(D), .Q(Q[1])); + +$_DFFE_PP_ ff2 (.C(C), .E(E), .D(D), .Q(Q[2])); +$_DFFE_PN_ ff3 (.C(C), .E(E), .D(D), .Q(Q[3])); +$_DFFE_NP_ ff4 (.C(C), .E(E), .D(D), .Q(Q[4])); + +$_DFF_PP0_ ff5 (.C(C), .R(R), .D(D), .Q(Q[5])); +$_DFF_PN0_ ff6 (.C(C), .R(R), .D(D), .Q(Q[6])); +$_DFF_NP0_ ff7 (.C(C), .R(R), .D(D), .Q(Q[7])); + +$_DFF_PP1_ ff8 (.C(C), .R(R), .D(D), .Q(Q[8])); +$_DFF_PN1_ ff9 (.C(C), .R(R), .D(D), .Q(Q[9])); +$_DFF_NP1_ ff10 (.C(C), .R(R), .D(D), .Q(Q[10])); + +$_DFFE_PP0P_ ff11 (.C(C), .R(R), .E(E), .D(D), .Q(Q[11])); +$_DFFE_PP0N_ ff12 (.C(C), .R(R), .E(E), .D(D), .Q(Q[12])); +$_DFFE_PN0P_ ff13 (.C(C), .R(R), .E(E), .D(D), .Q(Q[13])); +$_DFFE_NP0P_ ff14 (.C(C), .R(R), .E(E), .D(D), .Q(Q[14])); + +$_DFFE_PP1P_ ff15 (.C(C), .R(R), .E(E), .D(D), .Q(Q[15])); +$_DFFE_PP1N_ ff16 (.C(C), .R(R), .E(E), .D(D), .Q(Q[16])); +$_DFFE_PN1P_ ff17 (.C(C), .R(R), .E(E), .D(D), .Q(Q[17])); +$_DFFE_NP1P_ ff18 (.C(C), .R(R), .E(E), .D(D), .Q(Q[18])); + +$_DFFSR_PPP_ ff19 (.C(C), .R(R), .S(S), .D(D), .Q(Q[19])); +$_DFFSR_PPN_ ff20 (.C(C), .R(R), .S(S), .D(D), .Q(Q[20])); +$_DFFSR_PNP_ ff21 (.C(C), .R(R), .S(S), .D(D), .Q(Q[21])); +$_DFFSR_NPP_ ff22 (.C(C), .R(R), .S(S), .D(D), .Q(Q[22])); + +$_DFFSRE_PPPP_ ff23 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[23])); +$_DFFSRE_PPPN_ ff24 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[24])); +$_DFFSRE_PPNP_ ff25 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[25])); +$_DFFSRE_PNPP_ ff26 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[26])); +$_DFFSRE_NPPP_ ff27 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[27])); + +$_SDFF_PP0_ ff28 (.C(C), .R(R), .D(D), .Q(Q[28])); +$_SDFF_PN0_ ff29 (.C(C), .R(R), .D(D), .Q(Q[29])); +$_SDFF_NP0_ ff30 (.C(C), .R(R), .D(D), .Q(Q[30])); + +$_SDFF_PP1_ ff31 (.C(C), .R(R), .D(D), .Q(Q[31])); +$_SDFF_PN1_ ff32 (.C(C), .R(R), .D(D), .Q(Q[32])); +$_SDFF_NP1_ ff33 (.C(C), .R(R), .D(D), .Q(Q[33])); + +$_SDFFE_PP0P_ ff34 (.C(C), .R(R), .E(E), .D(D), .Q(Q[34])); +$_SDFFE_PP0N_ ff35 (.C(C), .R(R), .E(E), .D(D), .Q(Q[35])); +$_SDFFE_PN0P_ ff36 (.C(C), .R(R), .E(E), .D(D), .Q(Q[36])); +$_SDFFE_NP0P_ ff37 (.C(C), .R(R), .E(E), .D(D), .Q(Q[37])); + +$_SDFFE_PP1P_ ff38 (.C(C), .R(R), .E(E), .D(D), .Q(Q[38])); +$_SDFFE_PP1N_ ff39 (.C(C), .R(R), .E(E), .D(D), .Q(Q[39])); +$_SDFFE_PN1P_ ff40 (.C(C), .R(R), .E(E), .D(D), .Q(Q[40])); +$_SDFFE_NP1P_ ff41 (.C(C), .R(R), .E(E), .D(D), .Q(Q[41])); + +$_SDFFCE_PP0P_ ff42 (.C(C), .R(R), .E(E), .D(D), .Q(Q[42])); +$_SDFFCE_PP0N_ ff43 (.C(C), .R(R), .E(E), .D(D), .Q(Q[43])); +$_SDFFCE_PN0P_ ff44 (.C(C), .R(R), .E(E), .D(D), .Q(Q[44])); +$_SDFFCE_NP0P_ ff45 (.C(C), .R(R), .E(E), .D(D), .Q(Q[45])); + +$_SDFFCE_PP1P_ ff46 (.C(C), .R(R), .E(E), .D(D), .Q(Q[46])); +$_SDFFCE_PP1N_ ff47 (.C(C), .R(R), .E(E), .D(D), .Q(Q[47])); +$_SDFFCE_PN1P_ ff48 (.C(C), .R(R), .E(E), .D(D), .Q(Q[48])); +$_SDFFCE_NP1P_ ff49 (.C(C), .R(R), .E(E), .D(D), .Q(Q[49])); + +$_DLATCH_P_ ff50 (.E(E), .D(D), .Q(Q[50])); +$_DLATCH_N_ ff51 (.E(E), .D(D), .Q(Q[51])); + +$_DLATCH_PP0_ ff52 (.E(E), .R(R), .D(D), .Q(Q[52])); +$_DLATCH_PN0_ ff53 (.E(E), .R(R), .D(D), .Q(Q[53])); +$_DLATCH_NP0_ ff54 (.E(E), .R(R), .D(D), .Q(Q[54])); + +$_DLATCH_PP1_ ff55 (.E(E), .R(R), .D(D), .Q(Q[55])); +$_DLATCH_PN1_ ff56 (.E(E), .R(R), .D(D), .Q(Q[56])); +$_DLATCH_NP1_ ff57 (.E(E), .R(R), .D(D), .Q(Q[57])); + +$_DLATCHSR_PPP_ ff58 (.E(E), .R(R), .S(S), .D(D), .Q(Q[58])); +$_DLATCHSR_PPN_ ff59 (.E(E), .R(R), .S(S), .D(D), .Q(Q[59])); +$_DLATCHSR_PNP_ ff60 (.E(E), .R(R), .S(S), .D(D), .Q(Q[60])); +$_DLATCHSR_NPP_ ff61 (.E(E), .R(R), .S(S), .D(D), .Q(Q[61])); + +$_SR_PP_ ff62 (.R(R), .S(S), .Q(Q[62])); +$_SR_PN_ ff63 (.R(R), .S(S), .Q(Q[63])); +$_SR_NP_ ff64 (.R(R), .S(S), .Q(Q[64])); + +$_ALDFF_PP_ ff65 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[65])); +$_ALDFF_PN_ ff66 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[66])); +$_ALDFF_NP_ ff67 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[67])); + +$_ALDFFE_PPP_ ff68 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[68])); +$_ALDFFE_PPN_ ff69 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[69])); +$_ALDFFE_PNP_ ff70 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[70])); +$_ALDFFE_NPP_ ff71 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[71])); + +endmodule + +EOT + +design -save orig + +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x +design -load postopt + +select -assert-count 51 t:$_NOT_ +select -assert-count 2 t:$_DFF_P_ +select -assert-count 3 t:$_DFFE_PP_ +select -assert-count 3 t:$_DFF_PP0_ +select -assert-count 3 t:$_DFF_PP1_ +select -assert-count 4 t:$_DFFE_PP0P_ +select -assert-count 4 t:$_DFFE_PP1P_ +select -assert-count 4 t:$_DFFSR_PPP_ +select -assert-count 5 t:$_DFFSRE_PPPP_ +select -assert-count 3 t:$_SDFF_PP0_ +select -assert-count 3 t:$_SDFF_PP1_ +select -assert-count 4 t:$_SDFFE_PP0P_ +select -assert-count 4 t:$_SDFFE_PP1P_ +select -assert-count 4 t:$_SDFFCE_PP0P_ +select -assert-count 4 t:$_SDFFCE_PP1P_ +select -assert-count 2 t:$_DLATCH_P_ +select -assert-count 3 t:$_DLATCH_PP0_ +select -assert-count 3 t:$_DLATCH_PP1_ +select -assert-count 4 t:$_DLATCHSR_PPP_ +select -assert-count 3 t:$_SR_PP_ +select -assert-count 3 t:$_ALDFF_PP_ +select -assert-count 4 t:$_ALDFFE_PPP_ +select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFSR_PPP_ t:$_DFFSRE_PPPP_ t:$_SDFF_PP?_ t:$_SDFFE_PP?P_ t:$_SDFFCE_PP?P_ t:$_DLATCH_P_ t:$_DLATCH_PP?_ t:$_DLATCHSR_PPP_ t:$_SR_PP_ t:$_ALDFF_PP_ t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i + +# Now try it again, targetting the opposite cells. + +design -load orig + +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x +design -load postopt + +select -assert-count 135 t:$_NOT_ +select -assert-count 2 t:$_DFF_N_ +select -assert-count 3 t:$_DFFE_NN_ +select -assert-count 3 t:$_DFF_NN0_ +select -assert-count 3 t:$_DFF_NN1_ +select -assert-count 4 t:$_DFFE_NN0N_ +select -assert-count 4 t:$_DFFE_NN1N_ +select -assert-count 4 t:$_DFFSR_NNN_ +select -assert-count 5 t:$_DFFSRE_NNNN_ +select -assert-count 3 t:$_SDFF_NN0_ +select -assert-count 3 t:$_SDFF_NN1_ +select -assert-count 4 t:$_SDFFE_NN0N_ +select -assert-count 4 t:$_SDFFE_NN1N_ +select -assert-count 4 t:$_SDFFCE_NN0N_ +select -assert-count 4 t:$_SDFFCE_NN1N_ +select -assert-count 2 t:$_DLATCH_N_ +select -assert-count 3 t:$_DLATCH_NN0_ +select -assert-count 3 t:$_DLATCH_NN1_ +select -assert-count 4 t:$_DLATCHSR_NNN_ +select -assert-count 3 t:$_SR_NN_ +select -assert-count 3 t:$_ALDFF_NN_ +select -assert-count 4 t:$_ALDFFE_NNN_ +select -assert-none t:$_DFF_N_ t:$_DFFE_NN_ t:$_DFF_NN?_ t:$_DFFE_NN?N_ t:$_DFFSR_NNN_ t:$_DFFSRE_NNNN_ t:$_SDFF_NN?_ t:$_SDFFE_NN?N_ t:$_SDFFCE_NN?N_ t:$_DLATCH_N_ t:$_DLATCH_NN?_ t:$_DLATCHSR_NNN_ t:$_SR_NN_ t:$_ALDFF_NN_ t:$_ALDFFE_NNN_ t:$_NOT_ %% %n t:* %i + + +# Second test: make sure set/reset/enable are inverted before clock. + +design -reset + +read_verilog -icells <<EOT + +module top(input C, E, R, S, D, output [3:0] Q); + +$_DFFSRE_PPPP_ ff0 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[0])); +$_DFFSRE_NPPP_ ff1 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[1])); +$_DFFSRE_PNNN_ ff2 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[2])); +$_DFFSRE_NNNN_ ff3 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[3])); + +endmodule + +EOT + +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x +design -load postopt + +select -assert-count 6 t:$_NOT_ +select -assert-count 2 t:$_DFFSRE_PPPP_ +select -assert-count 2 t:$_DFFSRE_NNNN_ +select -assert-count 1 t:$_DFFSRE_PPPP_ n:ff0 %i +select -assert-count 1 t:$_DFFSRE_NNNN_ n:ff1 %i +select -assert-count 1 t:$_DFFSRE_PPPP_ n:ff2 %i +select -assert-count 1 t:$_DFFSRE_NNNN_ n:ff3 %i diff --git a/tests/techmap/dfflegalize_mince.ys b/tests/techmap/dfflegalize_mince.ys new file mode 100644 index 000000000..31c8d04fc --- /dev/null +++ b/tests/techmap/dfflegalize_mince.ys @@ -0,0 +1,53 @@ +read_verilog -icells <<EOT + +module top(input D, C, R, S, input [4:0] E, output [15:0] Q); +$_DFFE_PP_ ff0(.D(D), .C(C), .E(E[0]), .Q(Q[0])); +$_DFFE_PP0P_ ff1(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[1])); +$_DFFE_PP1P_ ff2(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[2])); +$_SDFFE_PP0P_ ff3(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[3])); +$_SDFFE_PP1P_ ff4(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[4])); +$_SDFFCE_PP0P_ ff5(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[5])); +$_SDFFCE_PP1P_ ff6(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[6])); +$_DFFSRE_PPPP_ ff7(.D(D), .C(C), .E(E[0]), .R(R), .S(S), .Q(Q[7])); +$_DFFE_PP_ ff8(.D(D), .C(C), .E(E[1]), .Q(Q[8])); +$_DFFE_PP0P_ ff9(.D(D), .C(C), .E(E[1]), .R(R), .Q(Q[9])); +$_DFFE_PP1P_ ff10(.D(D), .C(C), .E(E[2]), .R(R), .Q(Q[10])); +$_SDFFE_PP0P_ ff11(.D(D), .C(C), .E(E[2]), .R(R), .Q(Q[11])); +$_SDFFE_PP1P_ ff12(.D(D), .C(C), .E(E[3]), .R(R), .Q(Q[12])); +$_SDFFCE_PP0P_ ff13(.D(D), .C(C), .E(E[3]), .R(R), .Q(Q[13])); +$_SDFFCE_PP1P_ ff14(.D(D), .C(C), .E(E[4]), .R(R), .Q(Q[14])); +$_DFFSRE_PPPP_ ff15(.D(D), .C(C), .E(E[4]), .R(R), .S(S), .Q(Q[15])); +endmodule + +EOT + +design -save orig +equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3 +design -load postopt + +select -assert-count 4 t:$_DFFE_PP_ +select -assert-count 2 t:$_DFFE_PP0P_ +select -assert-count 2 t:$_DFFE_PP1P_ +select -assert-count 2 t:$_SDFFE_PP0P_ +select -assert-count 2 t:$_SDFFE_PP1P_ +select -assert-count 1 t:$_SDFFCE_PP0P_ +select -assert-count 1 t:$_SDFFCE_PP1P_ +select -assert-count 2 t:$_DFFSRE_PPPP_ +select -assert-count 10 t:$_MUX_ +select -assert-count 0 n:ff0 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff1 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff2 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff3 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff4 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff5 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff6 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff7 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff8 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff9 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff10 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff11 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff12 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff13 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff14 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff15 %ci %ci t:$_MUX_ %i +select -assert-none n:ff* t:$_MUX_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_minsrst.ys b/tests/techmap/dfflegalize_minsrst.ys new file mode 100644 index 000000000..689066147 --- /dev/null +++ b/tests/techmap/dfflegalize_minsrst.ys @@ -0,0 +1,43 @@ +read_verilog -icells <<EOT + +module top(input D, C, E, input [3:0] R, output [11:0] Q); +$_SDFF_PP0_ ff0(.D(D), .C(C), .R(R[0]), .Q(Q[0])); +$_SDFF_PP1_ ff1(.D(D), .C(C), .R(R[0]), .Q(Q[1])); +$_SDFFE_PP0P_ ff2(.D(D), .C(C), .R(R[0]), .E(E), .Q(Q[2])); +$_SDFFE_PP1P_ ff3(.D(D), .C(C), .R(R[0]), .E(E), .Q(Q[3])); +$_SDFFCE_PP0P_ ff4(.D(D), .C(C), .R(R[0]), .E(E), .Q(Q[4])); +$_SDFFCE_PP1P_ ff5(.D(D), .C(C), .R(R[0]), .E(E), .Q(Q[5])); +$_SDFF_PP0_ ff6(.D(D), .C(C), .R(R[1]), .Q(Q[6])); +$_SDFF_PP1_ ff7(.D(D), .C(C), .R(R[1]), .Q(Q[7])); +$_SDFFE_PP0P_ ff8(.D(D), .C(C), .R(R[2]), .E(E), .Q(Q[8])); +$_SDFFE_PP1P_ ff9(.D(D), .C(C), .R(R[2]), .E(E), .Q(Q[9])); +$_SDFFCE_PP0P_ ff10(.D(D), .C(C), .R(R[3]), .E(E), .Q(Q[10])); +$_SDFFCE_PP1P_ ff11(.D(D), .C(C), .R(R[3]), .E(E), .Q(Q[11])); +endmodule + +EOT + +design -save orig +equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3 +design -load postopt + +select -assert-count 5 t:$_SDFF_PP0_ +select -assert-count 1 t:$_SDFF_PP1_ +select -assert-count 1 t:$_SDFFE_PP0P_ +select -assert-count 1 t:$_SDFFE_PP1P_ +select -assert-count 3 t:$_SDFFCE_PP0P_ +select -assert-count 1 t:$_SDFFCE_PP1P_ +select -assert-count 8 t:$_MUX_ +select -assert-count 0 n:ff0 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff1 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff2 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff3 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff4 %ci %ci t:$_MUX_ %i +select -assert-count 0 n:ff5 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff6 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff7 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff8 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff9 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff10 %ci %ci t:$_MUX_ %i +select -assert-count 1 n:ff11 %ci %ci t:$_MUX_ %i +select -assert-none n:ff* t:$_MUX_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_sr.ys b/tests/techmap/dfflegalize_sr.ys new file mode 100644 index 000000000..ee59a6e3c --- /dev/null +++ b/tests/techmap/dfflegalize_sr.ys @@ -0,0 +1,74 @@ +read_verilog -icells <<EOT + +module sr(input R, S, output [2:0] Q); +$_SR_PP_ ff0 (.R(R), .S(S), .Q(Q[0])); +$_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1])); +$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2])); +endmodule + +EOT + +design -save orig +equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x + + +# Convert everything to SRs. + +design -load orig +dfflegalize -cell $_SR_PP_ x + +select -assert-count 2 t:$_NOT_ +select -assert-count 3 t:$_SR_PP_ +select -assert-none t:$_SR_PP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ x + +select -assert-count 2 t:$_NOT_ +select -assert-count 3 t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ x + +select -assert-count 5 t:$_NOT_ +select -assert-count 3 t:$_DLATCH_PP1_ +select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ x + +select -assert-count 2 t:$_NOT_ +select -assert-count 3 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ x + +select -assert-count 2 t:$_NOT_ +select -assert-count 3 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ x + +select -assert-count 2 t:$_NOT_ +select -assert-count 3 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_sr_init.ys b/tests/techmap/dfflegalize_sr_init.ys new file mode 100644 index 000000000..9d724de29 --- /dev/null +++ b/tests/techmap/dfflegalize_sr_init.ys @@ -0,0 +1,230 @@ +read_verilog -icells <<EOT + +module sr0(input R, S, (* init = 3'h0 *) output [2:0] Q); +$_SR_PP_ ff0 (.R(R), .S(S), .Q(Q[0])); +$_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1])); +$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2])); +endmodule + +module sr1(input R, S, (* init = 3'h7 *) output [2:0] Q); +$_SR_PP_ ff0 (.R(R), .S(S), .Q(Q[0])); +$_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1])); +$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2])); +endmodule + +module top(input R, S, output [5:0] Q); +sr0 sr0_(.S(S), .R(R), .Q(Q[2:0])); +sr1 sr1_(.S(S), .R(R), .Q(Q[5:3])); +endmodule + +EOT + +design -save orig +flatten +#equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_SR_PP_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 + + +# Convert everything to SRs. + +design -load orig +dfflegalize -cell $_SR_PP_ 0 + +select -assert-count 2 sr0/t:$_NOT_ +select -assert-count 5 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_SR_PP_ +select -assert-count 3 sr1/t:$_SR_PP_ +select -assert-count 0 sr0/t:$_ANDNOT_ +select -assert-count 1 sr1/t:$_ANDNOT_ +select -assert-count 0 sr0/t:$_AND_ +select -assert-count 1 sr1/t:$_AND_ +select -assert-count 0 sr0/t:$_OR_ +select -assert-count 1 sr1/t:$_OR_ +select -assert-none t:$_SR_PP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_SR_PP_ 1 + +select -assert-count 5 sr0/t:$_NOT_ +select -assert-count 2 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_SR_PP_ +select -assert-count 3 sr1/t:$_SR_PP_ +select -assert-count 1 sr0/t:$_ANDNOT_ +select -assert-count 0 sr1/t:$_ANDNOT_ +select -assert-count 1 sr0/t:$_AND_ +select -assert-count 0 sr1/t:$_AND_ +select -assert-count 1 sr0/t:$_OR_ +select -assert-count 0 sr1/t:$_OR_ +select -assert-none t:$_SR_PP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 0 + +select -assert-count 2 sr0/t:$_NOT_ +select -assert-count 5 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_DLATCH_PP0_ +select -assert-count 3 sr1/t:$_DLATCH_PP0_ +select -assert-count 0 sr0/t:$_ANDNOT_ +select -assert-count 1 sr1/t:$_ANDNOT_ +select -assert-count 0 sr0/t:$_AND_ +select -assert-count 1 sr1/t:$_AND_ +select -assert-count 0 sr0/t:$_OR_ +select -assert-count 1 sr1/t:$_OR_ +select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ 1 + +select -assert-count 5 sr0/t:$_NOT_ +select -assert-count 2 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_DLATCH_PP0_ +select -assert-count 3 sr1/t:$_DLATCH_PP0_ +select -assert-count 1 sr0/t:$_ANDNOT_ +select -assert-count 0 sr1/t:$_ANDNOT_ +select -assert-count 1 sr0/t:$_AND_ +select -assert-count 0 sr1/t:$_AND_ +select -assert-count 1 sr0/t:$_OR_ +select -assert-count 0 sr1/t:$_OR_ +select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 0 + +select -assert-count 8 sr0/t:$_NOT_ +select -assert-count 5 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_DLATCH_PP1_ +select -assert-count 3 sr1/t:$_DLATCH_PP1_ +select -assert-count 1 sr0/t:$_ANDNOT_ +select -assert-count 0 sr1/t:$_ANDNOT_ +select -assert-count 1 sr0/t:$_AND_ +select -assert-count 0 sr1/t:$_AND_ +select -assert-count 1 sr0/t:$_OR_ +select -assert-count 0 sr1/t:$_OR_ +select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ 1 + +select -assert-count 5 sr0/t:$_NOT_ +select -assert-count 8 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_DLATCH_PP1_ +select -assert-count 3 sr1/t:$_DLATCH_PP1_ +select -assert-count 0 sr0/t:$_ANDNOT_ +select -assert-count 1 sr1/t:$_ANDNOT_ +select -assert-count 0 sr0/t:$_AND_ +select -assert-count 1 sr1/t:$_AND_ +select -assert-count 0 sr0/t:$_OR_ +select -assert-count 1 sr1/t:$_OR_ +select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 0 + +select -assert-count 2 sr0/t:$_NOT_ +select -assert-count 5 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_DLATCHSR_PPP_ +select -assert-count 3 sr1/t:$_DLATCHSR_PPP_ +select -assert-count 0 sr0/t:$_ANDNOT_ +select -assert-count 1 sr1/t:$_ANDNOT_ +select -assert-count 0 sr0/t:$_AND_ +select -assert-count 1 sr1/t:$_AND_ +select -assert-count 0 sr0/t:$_OR_ +select -assert-count 1 sr1/t:$_OR_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ 1 + +select -assert-count 5 sr0/t:$_NOT_ +select -assert-count 2 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_DLATCHSR_PPP_ +select -assert-count 3 sr1/t:$_DLATCHSR_PPP_ +select -assert-count 1 sr0/t:$_ANDNOT_ +select -assert-count 0 sr1/t:$_ANDNOT_ +select -assert-count 1 sr0/t:$_AND_ +select -assert-count 0 sr1/t:$_AND_ +select -assert-count 1 sr0/t:$_OR_ +select -assert-count 0 sr1/t:$_OR_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 0 + +select -assert-count 2 sr0/t:$_NOT_ +select -assert-count 5 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_DFFSR_PPP_ +select -assert-count 3 sr1/t:$_DFFSR_PPP_ +select -assert-count 0 sr0/t:$_ANDNOT_ +select -assert-count 1 sr1/t:$_ANDNOT_ +select -assert-count 0 sr0/t:$_AND_ +select -assert-count 1 sr1/t:$_AND_ +select -assert-count 0 sr0/t:$_OR_ +select -assert-count 1 sr1/t:$_OR_ +select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 1 + +select -assert-count 5 sr0/t:$_NOT_ +select -assert-count 2 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_DFFSR_PPP_ +select -assert-count 3 sr1/t:$_DFFSR_PPP_ +select -assert-count 1 sr0/t:$_ANDNOT_ +select -assert-count 0 sr1/t:$_ANDNOT_ +select -assert-count 1 sr0/t:$_AND_ +select -assert-count 0 sr1/t:$_AND_ +select -assert-count 1 sr0/t:$_OR_ +select -assert-count 0 sr1/t:$_OR_ +select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 0 + +select -assert-count 2 sr0/t:$_NOT_ +select -assert-count 5 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_DFFSRE_PPPP_ +select -assert-count 3 sr1/t:$_DFFSRE_PPPP_ +select -assert-count 0 sr0/t:$_ANDNOT_ +select -assert-count 1 sr1/t:$_ANDNOT_ +select -assert-count 0 sr0/t:$_AND_ +select -assert-count 1 sr1/t:$_AND_ +select -assert-count 0 sr0/t:$_OR_ +select -assert-count 1 sr1/t:$_OR_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 1 + +select -assert-count 5 sr0/t:$_NOT_ +select -assert-count 2 sr1/t:$_NOT_ +select -assert-count 3 sr0/t:$_DFFSRE_PPPP_ +select -assert-count 3 sr1/t:$_DFFSRE_PPPP_ +select -assert-count 1 sr0/t:$_ANDNOT_ +select -assert-count 0 sr1/t:$_ANDNOT_ +select -assert-count 1 sr0/t:$_AND_ +select -assert-count 0 sr1/t:$_AND_ +select -assert-count 1 sr0/t:$_OR_ +select -assert-count 0 sr1/t:$_OR_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflibmap-sim.v b/tests/techmap/dfflibmap-sim.v new file mode 100644 index 000000000..1788a683b --- /dev/null +++ b/tests/techmap/dfflibmap-sim.v @@ -0,0 +1,22 @@ +module dffn(input CLK, D, output reg Q, output QN); + +always @(negedge CLK) + Q <= D; + +assign QN = ~Q; + +endmodule + +module dffsr(input CLK, D, CLEAR, PRESET, output reg Q, output QN); + +always @(posedge CLK, posedge CLEAR, posedge PRESET) + if (CLEAR) + Q <= 0; + else if (PRESET) + Q <= 1; + else + Q <= D; + +assign QN = ~Q; + +endmodule diff --git a/tests/techmap/dfflibmap.lib b/tests/techmap/dfflibmap.lib new file mode 100644 index 000000000..ce460877e --- /dev/null +++ b/tests/techmap/dfflibmap.lib @@ -0,0 +1,55 @@ +library(test) { + /* D-type flip-flop with asynchronous reset and preset */ + cell (dffn) { + area : 6; + ff("IQ", "IQN") { + next_state : "D"; + clocked_on : "!CLK"; + } + pin(D) { + direction : input; + } + pin(CLK) { + direction : input; + } + pin(Q) { + direction: output; + function : "IQ"; + } + pin(QN) { + direction: output; + function : "IQN"; + } + } + cell (dffsr) { + area : 6; + ff("IQ", "IQN") { + next_state : "D"; + clocked_on : "CLK"; + clear : "CLEAR"; + preset : "PRESET"; + clear_preset_var1 : L; + clear_preset_var2 : L; + } + pin(D) { + direction : input; + } + pin(CLK) { + direction : input; + } + pin(CLEAR) { + direction : input; + } + pin(PRESET) { + direction : input; + } + pin(Q) { + direction: output; + function : "IQ"; + } + pin(QN) { + direction: output; + function : "IQN"; + } + } +} diff --git a/tests/techmap/dfflibmap.ys b/tests/techmap/dfflibmap.ys new file mode 100644 index 000000000..04477eb14 --- /dev/null +++ b/tests/techmap/dfflibmap.ys @@ -0,0 +1,58 @@ +read_verilog -icells <<EOT + +module top(input C, D, S, R, output [9:0] Q); + +$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0])); +$_DFF_PP0_ ff1 (.C(C), .D(D), .R(R), .Q(Q[1])); +$_DFF_PP1_ ff2 (.C(C), .D(D), .R(R), .Q(Q[2])); +$_DFFSR_PPP_ ff3 (.C(C), .D(D), .R(R), .S(S), .Q(Q[3])); +$_DFFSR_NNN_ ff4 (.C(C), .D(D), .R(R), .S(S), .Q(Q[4])); + +assign Q[9:5] = ~Q[4:0]; + +endmodule + +EOT + +simplemap + +design -save orig + +#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -liberty dfflibmap.lib +#equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -prepare -liberty dfflibmap.lib +dfflibmap -prepare -liberty dfflibmap.lib +equiv_opt -map dfflibmap-sim.v -assert -multiclock dfflibmap -map-only -liberty dfflibmap.lib + +design -load orig +dfflibmap -liberty dfflibmap.lib +clean + +select -assert-count 4 t:$_NOT_ +select -assert-count 1 t:dffn +select -assert-count 4 t:dffsr +select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i + +design -load orig +dfflibmap -prepare -liberty dfflibmap.lib + +select -assert-count 9 t:$_NOT_ +select -assert-count 1 t:$_DFF_N_ +select -assert-count 4 t:$_DFFSR_PPP_ +select -assert-none t:$_DFF_N_ t:$_DFFSR_PPP_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflibmap -map-only -liberty dfflibmap.lib + +select -assert-count 5 t:$_NOT_ +select -assert-count 0 t:dffn +select -assert-count 1 t:dffsr + +design -load orig +dfflibmap -prepare -liberty dfflibmap.lib +dfflibmap -map-only -liberty dfflibmap.lib +clean + +select -assert-count 4 t:$_NOT_ +select -assert-count 1 t:dffn +select -assert-count 4 t:dffsr +select -assert-none t:dffn t:dffsr t:$_NOT_ %% %n t:* %i diff --git a/tests/techmap/dffunmap.ys b/tests/techmap/dffunmap.ys new file mode 100644 index 000000000..b813078ee --- /dev/null +++ b/tests/techmap/dffunmap.ys @@ -0,0 +1,100 @@ +read_verilog -icells << EOT + +module top(...); + +input C, R, E, S; +input [1:0] D; +output [20:0] Q; + +$dff #(.CLK_POLARITY(1'b0), .WIDTH(2)) ff0 (.CLK(C), .D(D), .Q(Q[1:0])); +$dffe #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b0), .WIDTH(2)) ff1 (.CLK(C), .EN(E), .D(D), .Q(Q[3:2])); +$sdff #(.CLK_POLARITY(1'b0), .WIDTH(2), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2)) ff2 (.CLK(C), .SRST(R), .D(D), .Q(Q[5:4])); +$sdffe #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2)) ff3 (.CLK(C), .EN(E), .SRST(R), .D(D), .Q(Q[7:6])); +$sdffce #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2)) ff4 (.CLK(C), .EN(E), .SRST(R), .D(D), .Q(Q[9:8])); +$adff #(.CLK_POLARITY(1'b0), .WIDTH(2), .ARST_POLARITY(1'b0), .ARST_VALUE(2'h2)) ff5 (.CLK(C), .ARST(R), .D(D), .Q(Q[11:10])); +$adffe #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2)) ff6 (.CLK(C), .EN(E), .ARST(R), .D(D), .Q(Q[13:12])); +$dffsr #(.CLK_POLARITY(1'b0), .WIDTH(2), .CLR_POLARITY(1'b0), .SET_POLARITY(1'b1)) ff7 (.CLK(C), .CLR({R, S}), .SET({S, R}), .D(D), .Q(Q[15:14])); +$dffsre #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0)) ff8 (.CLK(C), .EN(E), .CLR({R, R}), .SET({S, S}), .D(D), .Q(Q[17:16])); + +endmodule + +EOT + +design -save orig + +equiv_opt -assert -async2sync dffunmap +design -load postopt +select -assert-none t:$sdff t:$dffe t:$adffe t:$sdffe t:$sdffce t:$dffsre +select -assert-count 5 t:$dff +select -assert-count 2 t:$adff +select -assert-count 2 t:$dffsr + +design -load orig + +equiv_opt -assert -async2sync dffunmap -ce-only +design -load postopt +select -assert-none t:$dffe t:$adffe t:$sdffe t:$sdffce t:$dffsre +select -assert-count 3 t:$dff +select -assert-count 2 t:$sdff +select -assert-count 2 t:$adff +select -assert-count 2 t:$dffsr + +design -load orig + +equiv_opt -assert -async2sync dffunmap -srst-only +design -load postopt +select -assert-none t:$sdff t:$sdffe t:$sdffce +select -assert-count 3 t:$dff +select -assert-count 2 t:$dffe +select -assert-count 1 t:$adff +select -assert-count 1 t:$adffe +select -assert-count 1 t:$dffsr +select -assert-count 1 t:$dffsre + +design -load orig +simplemap + +equiv_opt -assert -async2sync dffunmap +design -load postopt +select -assert-none t:$_SDFF* t:$_DFFE_* t:$_DFFSRE_* +select -assert-count 10 t:$_DFF_N_ +select -assert-count 1 t:$_DFF_NP0_ +select -assert-count 1 t:$_DFF_NN0_ +select -assert-count 1 t:$_DFF_NP1_ +select -assert-count 1 t:$_DFF_NN1_ +select -assert-count 2 t:$_DFFSR_NPN_ +select -assert-count 2 t:$_DFFSR_NNP_ + +design -load orig +simplemap + +equiv_opt -assert -async2sync dffunmap -ce-only +design -load postopt +select -assert-none t:$_SDFFE_* t:$_SDFFCE_* t:$_DFFE_* t:$_DFFSRE_* +select -assert-count 6 t:$_DFF_N_ +select -assert-count 1 t:$_SDFF_NP0_ +select -assert-count 1 t:$_SDFF_NN0_ +select -assert-count 1 t:$_SDFF_NP1_ +select -assert-count 1 t:$_SDFF_NN1_ +select -assert-count 1 t:$_DFF_NP0_ +select -assert-count 1 t:$_DFF_NN0_ +select -assert-count 1 t:$_DFF_NP1_ +select -assert-count 1 t:$_DFF_NN1_ +select -assert-count 2 t:$_DFFSR_NPN_ +select -assert-count 2 t:$_DFFSR_NNP_ + +design -load orig +simplemap + +equiv_opt -assert -async2sync dffunmap -srst-only +design -load postopt +select -assert-none t:$sdff t:$sdffe t:$sdffce +select -assert-count 6 t:$_DFF_N_ +select -assert-count 2 t:$_DFFE_NP_ +select -assert-count 2 t:$_DFFE_NN_ +select -assert-count 1 t:$_DFF_NN0_ +select -assert-count 1 t:$_DFF_NN1_ +select -assert-count 1 t:$_DFFE_NP0P_ +select -assert-count 1 t:$_DFFE_NP1P_ +select -assert-count 2 t:$_DFFSR_NPN_ +select -assert-count 2 t:$_DFFSRE_NNPP_ diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys index df029b3a0..f8e6bc374 100644 --- a/tests/techmap/iopadmap.ys +++ b/tests/techmap/iopadmap.ys @@ -169,7 +169,7 @@ sub s2(.i(i[1]), .o(w[1])); assign o = oe ? w : 2'bz; endmodule -module c(input i, oe, (* init=2'b00 *) inout io, output o1, o2); +module c(input i, oe, (* init=1'b0 *) inout io, output o1, o2); assign io = oe ? i : 1'bz; assign {o1,o2} = {io,io}; endmodule @@ -182,5 +182,5 @@ select -assert-count 1 a/c:s %co a/a:init=1'b1 %i select -assert-count 1 a/a:init select -assert-count 1 b/c:s* %co %a b/a:init=2'b1x %i select -assert-count 1 b/a:init -select -assert-count 1 c/t:iobuf %co c/a:init=2'b00 %i +select -assert-count 1 c/t:iobuf %co c/a:init=1'b0 %i select -assert-count 1 c/a:init diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index e2c6303da..b486de5c7 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -1,8 +1,8 @@ #!/bin/bash -set -ev +set -e -../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v +../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'read_verilog mem_simple_4x1_uut.v; proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v diff --git a/tests/techmap/pmux2mux.ys b/tests/techmap/pmux2mux.ys new file mode 100644 index 000000000..1714a6b87 --- /dev/null +++ b/tests/techmap/pmux2mux.ys @@ -0,0 +1,15 @@ +read_verilog -icells << EOT +module top(...); + +input [3:0] A; +input [3:0] B0; +input [3:0] B1; +input [1:0] S; +output [3:0] O; + +\$pmux #(.WIDTH(4), .S_WIDTH(2)) pm (.A(A), .B({B1, B0}), .S(S), .Y(O)); + +endmodule +EOT + +equiv_opt techmap -map +/pmux2mux.v diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh index 30c79bf03..564d678fa 100644 --- a/tests/techmap/recursive_runtest.sh +++ b/tests/techmap/recursive_runtest.sh @@ -1,3 +1,3 @@ -set -ev +set -e -../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v +../../yosys -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh index c16f204d9..581847ab0 100755 --- a/tests/techmap/run-test.sh +++ b/tests/techmap/run-test.sh @@ -1,20 +1,4 @@ #!/usr/bin/env bash -set -e -{ -echo "all::" -for x in *.ys; do - echo "all:: run-$x" - echo "run-$x:" - echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -e 'select out of bounds' $x" -done -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s > ${s%.sh}.log 2>&1" - fi -done -} > run-test.mk -exec ${MAKE:-make} -f run-test.mk +set -eu +source ../gen-tests-makefile.sh +run_tests --yosys-scripts --bash --yosys-args "-e 'select out of bounds'" diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys index eb29680f6..f749e79b2 100644 --- a/tests/techmap/shiftx2mux.ys +++ b/tests/techmap/shiftx2mux.ys @@ -74,12 +74,6 @@ design -save gold design -load gold -techmap -D NO_LSB_FIRST_SHIFT_SHIFTX -abc -lut 6 -select -assert-min 17 t:$lut - - -design -load gold techmap abc -lut 6 select -assert-count 16 t:$lut @@ -92,12 +86,6 @@ sat -verify -prove-asserts -show-ports miter design -load gold -techmap -D NO_LSB_FIRST_SHIFT_SHIFTX -abc9 -lut 6 -select -assert-min 17 t:$lut - - -design -load gold techmap abc9 -lut 6 select -assert-count 16 t:$lut diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys index 3527840b9..bc07f40e6 100644 --- a/tests/techmap/zinit.ys +++ b/tests/techmap/zinit.ys @@ -20,7 +20,8 @@ EOT equiv_opt -assert -multiclock zinit design -load postopt -select -assert-count 20 t:$_NOT_ +select -assert-count 16 t:$_NOT_ +select -assert-count 4 t:$xor select -assert-count 1 w:unused a:init %i select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??1_ %i @@ -52,7 +53,7 @@ design -load postopt select -assert-count 0 t:$_NOT_ select -assert-count 1 w:unused a:init %i -select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i +select -assert-count 1 w:Q a:init=13'bx00x100000000 %i select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??0_ %i select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFF_??1_ %i @@ -95,7 +96,7 @@ EOT zinit select -assert-count 48 t:$_NOT_ -select -assert-count 1 w:Q a:init=24'bx %i +select -assert-count 0 w:Q a:init %i select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFFE_??1P_ %i select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFFE_??0P_ %i select -assert-count 4 c:dff8 c:dff10 c:dff12 c:dff14 %% t:$_SDFF_??1_ %i @@ -142,7 +143,7 @@ EOT zinit select -assert-count 0 t:$_NOT_ -select -assert-count 1 w:Q a:init=24'bx %i +select -assert-count 1 w:Q a:init=24'b0 %i select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFFE_??0P_ %i select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFFE_??1P_ %i select -assert-count 4 c:dff8 c:dff10 c:dff12 c:dff14 %% t:$_SDFF_??0_ %i |