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-rwxr-xr-xtests/tools/autotest.sh5
1 files changed, 3 insertions, 2 deletions
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 86a90793e..920474a84 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -132,13 +132,13 @@ do
fn=$(basename $fn)
bn=$(basename $bn)
+ rm -f ${bn}_ref.fir
if [[ "$ext" == "v" ]]; then
egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
else
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
frontend="verilog -noblackbox"
fi
- rm -f ${bn}_ref.fir
if [ ! -f ../${bn}_tb.v ]; then
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
@@ -147,7 +147,8 @@ do
fi
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
- "$toolsdir"/../../techlibs/common/simlib.v
+ "$toolsdir"/../../techlibs/common/simlib.v \
+ "$toolsdir"/../../techlibs/common/simcells.v
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
test_count=0