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Diffstat (limited to 'tests/various/sim_const.ys')
| -rw-r--r-- | tests/various/sim_const.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/various/sim_const.ys b/tests/various/sim_const.ys new file mode 100644 index 000000000..d778b92cd --- /dev/null +++ b/tests/various/sim_const.ys @@ -0,0 +1,13 @@ +read_verilog <<EOT + +module top(input clk, output reg [1:0] q); + wire [1:0] x = 2'b10; + always @(posedge clk) + q <= x & 2'b11; +endmodule +EOT + +proc +sim -clock clk -n 1 -w top +select -assert-count 1 a:init=2'b10 top/q %i + |