diff options
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/.gitignore | 1 | ||||
| -rw-r--r-- | tests/various/muxpack.ys | 30 | ||||
| -rw-r--r-- | tests/various/opt_expr.ys | 223 | ||||
| -rw-r--r-- | tests/various/opt_rmdff.v | 50 | ||||
| -rw-r--r-- | tests/various/opt_rmdff.ys | 26 | ||||
| -rw-r--r-- | tests/various/pmgen_reduce.ys | 21 | ||||
| -rwxr-xr-x | tests/various/run-test.sh | 16 | ||||
| -rw-r--r-- | tests/various/shregmap.ys | 22 | ||||
| -rw-r--r-- | tests/various/wreduce.ys | 33 |
9 files changed, 92 insertions, 330 deletions
diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 31078b298..4b286fd61 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -2,3 +2,4 @@ /*.out /write_gzip.v /write_gzip.v.gz +/run-test.mk diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index af23fcec8..3e90419af 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -6,7 +6,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -21,7 +21,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -52,7 +52,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate @@ -67,7 +67,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -82,7 +82,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -97,7 +97,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -112,7 +112,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -127,7 +127,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -142,7 +142,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 7 t:$mux select -assert-count 0 t:$pmux design -stash gate @@ -157,7 +157,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 4 t:$mux select -assert-count 0 t:$pmux design -stash gate @@ -172,7 +172,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 3 t:$mux select -assert-count 0 t:$pmux design -stash gate @@ -204,7 +204,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate @@ -222,7 +222,7 @@ opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -240,7 +240,7 @@ opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate @@ -258,7 +258,7 @@ opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate diff --git a/tests/various/opt_expr.ys b/tests/various/opt_expr.ys deleted file mode 100644 index f0306efa1..000000000 --- a/tests/various/opt_expr.ys +++ /dev/null @@ -1,223 +0,0 @@ - -read_verilog <<EOT -module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = (i << 4) + j; -endmodule -EOT - -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -########## - -# alumacc version of above -design -reset -read_verilog <<EOT -module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = (i << 4) + j; -endmodule -EOT - -alumacc -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i - -########## - -design -reset -read_verilog <<EOT -module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); - assign o = (i << 4) + j; -endmodule -EOT - -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -########## - -# alumacc version of above -design -reset -read_verilog <<EOT -module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); - assign o = (i << 4) + j; -endmodule -EOT - -alumacc -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i - -########## - -design -reset -read_verilog <<EOT -module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = j - (i << 4); -endmodule -EOT - -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i - -########## - -# alumacc version of above -design -reset -read_verilog <<EOT -module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = j - (i << 4); -endmodule -EOT - -alumacc -equiv_opt -assert opt_expr -fine -design -load postopt - -dump -select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i - -########## - -design -reset -read_verilog <<EOT -module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); - assign o = j - (i << 4); -endmodule -EOT - -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i - -########## - -# alumacc version of above -design -reset -read_verilog <<EOT -module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); - assign o = j - (i << 4); -endmodule -EOT - -alumacc -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i - -########## - -design -reset -read_verilog <<EOT -module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = (i << 4) - j; -endmodule -EOT - -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i - -########## - -# alumacc version of above -design -reset -read_verilog <<EOT -module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); - assign o = (i << 4) - j; -endmodule -EOT - -alumacc -opt_expr -fine -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i - -########## - -design -reset -read_verilog <<EOT -module opt_expr_sub_test4(input [3:0] i, output [8:0] o); - assign o = 5'b00010 - i; -endmodule -EOT - -wreduce -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -########## - -# alumacc version of above -design -reset -read_verilog <<EOT -module opt_expr_sub_test4(input [3:0] i, output [8:0] o); - assign o = 5'b00010 - i; -endmodule -EOT - -wreduce -alumacc -equiv_opt -assert opt_expr -fine -design -load postopt - -select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -########### - -design -reset -read_verilog -icells <<EOT -module opt_expr_alu_test_ci0_bi0(input [7:0] a, input [3:0] b, output [8:0] x, y, co); - \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b0), .X(x), .Y(y), .CO(co)); -endmodule -EOT -check - -equiv_opt -assert opt_expr -fine -design -load postopt -select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -########### - -design -reset -read_verilog -icells <<EOT -module opt_expr_alu_test_ci1_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co); - \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b1), .BI(1'b1), .X(x), .Y(y), .CO(co)); -endmodule -EOT -check - -equiv_opt opt_expr -fine -design -load postopt -select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i - -########### - -design -reset -read_verilog -icells <<EOT -module opt_expr_alu_test_ci0_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co); - \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b1), .X(x), .Y(y), .CO(co)); -endmodule -EOT -check - -equiv_opt opt_expr -fine -design -load postopt -select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i diff --git a/tests/various/opt_rmdff.v b/tests/various/opt_rmdff.v deleted file mode 100644 index b1c06703c..000000000 --- a/tests/various/opt_rmdff.v +++ /dev/null @@ -1,50 +0,0 @@ -module opt_rmdff_test (input C, input D, input E, output [29:0] Q); -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active -(* init = "1'b1" *) wire Q1; assign Q[1] = Q1; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q1)); // EN is never active -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); // EN is always active -(* init = "1'b0" *) wire Q4; assign Q[4] = Q4; -\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q4)); // EN is always active -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); // EN is never active -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); // EN is don't care -(* init = "1'b0" *) wire Q7; assign Q[7] = Q7; -\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q7)); // EN is non constant - -\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); // EN is never active -(* init = "1'b1" *) wire Q9; assign Q[9] = Q9; -\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q9)); // EN is never active -\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); // EN is don't care -\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); // EN is always active -(* init = "1'b0" *) wire Q12; assign Q[12] = Q12; -\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q12)); // EN is always active - -\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); // EN is never active -(* init = "1'b1" *) wire Q14; assign Q[14] = Q14; -\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q14)); // EN is never active -\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); // EN is don't care -\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); // EN is always active -(* init = "1'b0" *) wire Q17; assign Q[17] = Q17; -\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q17)); // EN is always active - -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(E), .Q(Q[18])); // CLK is constant -(* init = "1'b1" *) wire Q19; assign Q[19] = Q19; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q19)); // CLK is constant -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[20])); // D is undriven, Q has no initial value -(* init = "1'b0" *) wire Q21; assign Q[21] = Q21; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q21)); // D is undriven, Q has initial value -//\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active -// // (TODO, Q starts with 1'bx and becomes 1'b0) -(* init = "1'b0" *) wire Q23; assign Q[23] = Q23; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q23)); // D is constant, initial Q value same as D, EN is always active -(* init = "1'b1" *) wire Q24; assign Q[24] = Q24; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q24)); // D is constant, initial Q value NOT same as D, EN is always active -(* init = "1'b1" *) wire Q25; assign Q[25] = Q25; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q25)); // D is constant, EN is never active -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(E), .Q(Q[28])); // EN is nonconst, but no initial value -(* init = "1'b1" *) wire Q29; assign Q[29] = Q29; -\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q29)); // EN is always active, but with initial value - -endmodule diff --git a/tests/various/opt_rmdff.ys b/tests/various/opt_rmdff.ys deleted file mode 100644 index 081f81782..000000000 --- a/tests/various/opt_rmdff.ys +++ /dev/null @@ -1,26 +0,0 @@ -read_verilog -icells opt_rmdff.v -prep -design -stash gold -read_verilog -icells opt_rmdff.v -proc -opt_rmdff - -select -assert-count 0 c:remove* -select -assert-min 7 c:keep* -select -assert-count 0 t:$dffe 7:$_DFFE_* %u c:noenable* %i - -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -equiv_make gold gate equiv -hierarchy -top equiv -equiv_simple -undef -equiv_status -assert - -design -load gold -stat - -design -load gate -stat diff --git a/tests/various/pmgen_reduce.ys b/tests/various/pmgen_reduce.ys new file mode 100644 index 000000000..c214d3f25 --- /dev/null +++ b/tests/various/pmgen_reduce.ys @@ -0,0 +1,21 @@ +test_pmgen -generate reduce +hierarchy -top pmtest_test_pmgen_pm_reduce +flatten; opt_clean + +design -save gold +test_pmgen -reduce_chain +design -stash gate + +design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce +design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce +miter -equiv -flatten -make_assert gold gate miter +sat -verify -prove-asserts miter + +design -load gold +test_pmgen -reduce_tree +design -stash gate + +design -copy-from gold -as gold pmtest_test_pmgen_pm_reduce +design -copy-from gate -as gate pmtest_test_pmgen_pm_reduce +miter -equiv -flatten -make_assert gold gate miter +sat -verify -prove-asserts miter diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh index 92b905765..ea56b70f0 100755 --- a/tests/various/run-test.sh +++ b/tests/various/run-test.sh @@ -1,12 +1,20 @@ #!/usr/bin/env bash set -e +{ +echo "all::" for x in *.ys; do - echo "Running $x.." - ../../yosys -ql ${x%.ys}.log $x + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then - echo "Running $s.." - bash $s + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" fi done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index d644a88aa..0e5fe882b 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -11,7 +11,7 @@ shregmap -init opt -stat +# stat # show -width select -assert-count 1 t:$_DFF_P_ select -assert-count 2 t:$__SHREG_DFF_P_ @@ -26,11 +26,11 @@ prep miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 5 miter -design -load gold -stat +#design -load gold +#stat -design -load gate -stat +#design -load gate +#stat ########## @@ -43,9 +43,9 @@ design -save gold simplemap t:$dff t:$dffe shregmap -tech xilinx -stat +#stat # show -width -write_verilog -noexpr -norename +# write_verilog -noexpr -norename select -assert-count 1 t:$_DFF_P_ select -assert-count 2 t:$__XILINX_SHREG_ @@ -59,8 +59,8 @@ prep miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 5 miter -design -load gold -stat +# design -load gold +# stat -design -load gate -stat +# design -load gate +# stat diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index 4257292f5..2e0812c48 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -36,7 +36,6 @@ design -save gold opt_expr wreduce -dump select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i design -stash gate @@ -46,3 +45,35 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +########## + +# Testcase from: https://github.com/YosysHQ/yosys/commit/25680f6a078bb32f157bd580705656496717bafb +design -reset +read_verilog <<EOT +module top( + input clk, + input rst, + input [2:0] a, + output [1:0] b +); + reg [2:0] b_reg; + initial begin + b_reg <= 3'b0; + end + + assign b = b_reg[1:0]; + always @(posedge clk or posedge rst) begin + if(rst) begin + b_reg <= 3'b0; + end else begin + b_reg <= a; + end + end +endmodule +EOT + +proc +wreduce + +select -assert-count 1 t:$adff r:ARST_VALUE=2'b00 %i |