3 files changed, 4 insertions, 4 deletions
diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v
index f55ef2316..8c9fb2926 100644
--- a/tests/various/attrib07_func_call.v
+++ b/tests/various/attrib07_func_call.v
@@ -11,7 +11,7 @@ module foo(clk, rst, inp_a, inp_b, out);
   input  wire rst;
   input  wire [7:0] inp_a;
   input  wire [7:0] inp_b;
-  output wire [7:0] out;
+  output reg  [7:0] out;
 
   always @(posedge clk)
     if (rst) out <= 0;
diff --git a/tests/various/constmsk_testmap.v b/tests/various/constmsk_testmap.v
index fab1b1bbc..b6809c7c0 100644
--- a/tests/various/constmsk_testmap.v
+++ b/tests/various/constmsk_testmap.v
@@ -1,7 +1,7 @@
 (* techmap_celltype = "$reduce_or" *)
 module my_opt_reduce_or(...);
     parameter A_SIGNED = 0;
-    parameter A_WIDTH = 1;
+    parameter A_WIDTH = 2;
     parameter Y_WIDTH = 1;
 
     input [A_WIDTH-1:0] A;
diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
index 604c2c976..dc828eda7 100644
--- a/tests/various/shregmap.v
+++ b/tests/various/shregmap.v
@@ -13,7 +13,7 @@ assign q = {shift2[3], shift1[3]};
 endmodule
 
 module $__SHREG_DFF_P_(input C, D, output Q);
-parameter DEPTH = 1;
+parameter DEPTH = 2;
 parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
 reg [DEPTH-1:0] r = INIT;
 always @(posedge C) 
@@ -38,7 +38,7 @@ endmodule
 module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
 parameter CLKPOL = 1;
 parameter ENPOL = 1;
-parameter DEPTH = 1;
+parameter DEPTH = 2;
 parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
 reg [DEPTH-1:0] r = INIT;
 wire clk = C ^ CLKPOL;