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-rw-r--r--tests/various/const_arg_loop.v44
-rw-r--r--tests/various/const_arg_loop.ys1
-rw-r--r--tests/various/const_func.v12
-rw-r--r--tests/various/equiv_opt_undef.ys35
4 files changed, 92 insertions, 0 deletions
diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v
new file mode 100644
index 000000000..85318562f
--- /dev/null
+++ b/tests/various/const_arg_loop.v
@@ -0,0 +1,44 @@
+module top;
+ function automatic [31:0] operation1;
+ input [4:0] rounds;
+ input integer num;
+ integer i;
+ begin
+ begin : shadow
+ integer rounds;
+ rounds = 0;
+ end
+ for (i = 0; i < rounds; i = i + 1)
+ num = num * 2;
+ operation1 = num;
+ end
+ endfunction
+
+ function automatic [31:0] operation2;
+ input [4:0] var;
+ input integer num;
+ begin
+ var[0] = var[0] ^ 1;
+ operation2 = num * var;
+ end
+ endfunction
+
+ wire [31:0] a;
+ assign a = 2;
+
+ parameter A = 3;
+
+ wire [31:0] x1;
+ assign x1 = operation1(A, a);
+
+ wire [31:0] x2;
+ assign x2 = operation2(A, a);
+
+// `define VERIFY
+`ifdef VERIFY
+ assert property (a == 2);
+ assert property (A == 3);
+ assert property (x1 == 16);
+ assert property (x2 == 4);
+`endif
+endmodule
diff --git a/tests/various/const_arg_loop.ys b/tests/various/const_arg_loop.ys
new file mode 100644
index 000000000..b039bda10
--- /dev/null
+++ b/tests/various/const_arg_loop.ys
@@ -0,0 +1 @@
+read_verilog const_arg_loop.v
diff --git a/tests/various/const_func.v b/tests/various/const_func.v
index 76cdc385d..541e63b19 100644
--- a/tests/various/const_func.v
+++ b/tests/various/const_func.v
@@ -53,6 +53,15 @@ module top(out);
c1, c2, c3, c4,
d1, d2, d3, d4};
+ function signed [31:0] negate;
+ input integer inp;
+ negate = ~inp;
+ endfunction
+ parameter W = 10;
+ parameter X = 3;
+ localparam signed Y = $floor(W / X);
+ localparam signed Z = negate($floor(W / X));
+
// `define VERIFY
`ifdef VERIFY
assert property (a1 == 0);
@@ -71,5 +80,8 @@ module top(out);
assert property (d2 == 0);
assert property (d3 == 1);
assert property (d4 == 1);
+
+ assert property (Y == 3);
+ assert property (Z == ~3);
`endif
endmodule
diff --git a/tests/various/equiv_opt_undef.ys b/tests/various/equiv_opt_undef.ys
new file mode 100644
index 000000000..5d2c60d0a
--- /dev/null
+++ b/tests/various/equiv_opt_undef.ys
@@ -0,0 +1,35 @@
+read_ilang << EOT
+
+module \top
+ wire $a
+ wire $b
+ wire input 1 \D
+ wire input 2 \EN
+ wire output 3 \Q
+ cell $mux $x
+ parameter \WIDTH 1
+ connect \A \Q
+ connect \B \D
+ connect \S \EN
+ connect \Y $a
+ end
+ cell $ff $y
+ parameter \WIDTH 1
+ connect \D $a
+ connect \Q $b
+ end
+ cell $and $z
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $b
+ connect \B 1'x
+ connect \Y \Q
+ end
+end
+
+EOT
+
+equiv_opt -assert -undef ls