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-rw-r--r--tests/various/const_arg_loop.v44
-rw-r--r--tests/various/const_arg_loop.ys1
-rw-r--r--tests/various/const_func.v87
-rw-r--r--tests/various/const_func.ys1
-rw-r--r--tests/various/const_func_block_var.v23
-rw-r--r--tests/various/const_func_block_var.ys1
-rw-r--r--tests/various/equiv_opt_undef.ys35
-rw-r--r--tests/various/integer_range_bad_syntax.ys6
-rw-r--r--tests/various/integer_real_bad_syntax.ys6
-rw-r--r--tests/various/logic_param_simple.ys9
-rw-r--r--tests/various/plugin.cc2
-rw-r--r--tests/various/signed.ys28
12 files changed, 242 insertions, 1 deletions
diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v
new file mode 100644
index 000000000..85318562f
--- /dev/null
+++ b/tests/various/const_arg_loop.v
@@ -0,0 +1,44 @@
+module top;
+ function automatic [31:0] operation1;
+ input [4:0] rounds;
+ input integer num;
+ integer i;
+ begin
+ begin : shadow
+ integer rounds;
+ rounds = 0;
+ end
+ for (i = 0; i < rounds; i = i + 1)
+ num = num * 2;
+ operation1 = num;
+ end
+ endfunction
+
+ function automatic [31:0] operation2;
+ input [4:0] var;
+ input integer num;
+ begin
+ var[0] = var[0] ^ 1;
+ operation2 = num * var;
+ end
+ endfunction
+
+ wire [31:0] a;
+ assign a = 2;
+
+ parameter A = 3;
+
+ wire [31:0] x1;
+ assign x1 = operation1(A, a);
+
+ wire [31:0] x2;
+ assign x2 = operation2(A, a);
+
+// `define VERIFY
+`ifdef VERIFY
+ assert property (a == 2);
+ assert property (A == 3);
+ assert property (x1 == 16);
+ assert property (x2 == 4);
+`endif
+endmodule
diff --git a/tests/various/const_arg_loop.ys b/tests/various/const_arg_loop.ys
new file mode 100644
index 000000000..b039bda10
--- /dev/null
+++ b/tests/various/const_arg_loop.ys
@@ -0,0 +1 @@
+read_verilog const_arg_loop.v
diff --git a/tests/various/const_func.v b/tests/various/const_func.v
new file mode 100644
index 000000000..541e63b19
--- /dev/null
+++ b/tests/various/const_func.v
@@ -0,0 +1,87 @@
+module Example(outA, outB, outC, outD);
+ parameter OUTPUT = "FOO";
+ output wire [23:0] outA;
+ output wire [23:0] outB;
+ output reg outC, outD;
+ function automatic [23:0] flip;
+ input [23:0] inp;
+ flip = ~inp;
+ endfunction
+
+ generate
+ if (flip(OUTPUT) == flip("BAR"))
+ assign outA = OUTPUT;
+ else
+ assign outA = 0;
+
+ case (flip(OUTPUT))
+ flip("FOO"): assign outB = OUTPUT;
+ flip("BAR"): assign outB = 0;
+ flip("BAZ"): assign outB = "HI";
+ endcase
+
+ genvar i;
+ initial outC = 0;
+ for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1)
+ if (i + 1 == flip(flip("O")))
+ initial outC = 1;
+ endgenerate
+
+ integer j;
+ initial begin
+ outD = 1;
+ for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1)
+ if (j + 1 == flip(flip("O")))
+ outD = 0;
+ end
+endmodule
+
+module top(out);
+ wire [23:0] a1, a2, a3, a4;
+ wire [23:0] b1, b2, b3, b4;
+ wire c1, c2, c3, c4;
+ wire d1, d2, d3, d4;
+ Example e1(a1, b1, c1, d1);
+ Example #("FOO") e2(a2, b2, c2, d2);
+ Example #("BAR") e3(a3, b3, c3, d3);
+ Example #("BAZ") e4(a4, b4, c4, d4);
+
+ output wire [24 * 8 - 1 + 4 :0] out;
+ assign out = {
+ a1, a2, a3, a4,
+ b1, b2, b3, b4,
+ c1, c2, c3, c4,
+ d1, d2, d3, d4};
+
+ function signed [31:0] negate;
+ input integer inp;
+ negate = ~inp;
+ endfunction
+ parameter W = 10;
+ parameter X = 3;
+ localparam signed Y = $floor(W / X);
+ localparam signed Z = negate($floor(W / X));
+
+// `define VERIFY
+`ifdef VERIFY
+ assert property (a1 == 0);
+ assert property (a2 == 0);
+ assert property (a3 == "BAR");
+ assert property (a4 == 0);
+ assert property (b1 == "FOO");
+ assert property (b2 == "FOO");
+ assert property (b3 == 0);
+ assert property (b4 == "HI");
+ assert property (c1 == 1);
+ assert property (c2 == 1);
+ assert property (c3 == 0);
+ assert property (c4 == 0);
+ assert property (d1 == 0);
+ assert property (d2 == 0);
+ assert property (d3 == 1);
+ assert property (d4 == 1);
+
+ assert property (Y == 3);
+ assert property (Z == ~3);
+`endif
+endmodule
diff --git a/tests/various/const_func.ys b/tests/various/const_func.ys
new file mode 100644
index 000000000..5e3c04105
--- /dev/null
+++ b/tests/various/const_func.ys
@@ -0,0 +1 @@
+read_verilog const_func.v
diff --git a/tests/various/const_func_block_var.v b/tests/various/const_func_block_var.v
new file mode 100644
index 000000000..98e83aa5b
--- /dev/null
+++ b/tests/various/const_func_block_var.v
@@ -0,0 +1,23 @@
+module top(out);
+ function integer operation;
+ input integer num;
+ begin
+ operation = 0;
+ begin : op_i
+ integer i;
+ for (i = 0; i < 2; i = i + 1)
+ begin : op_j
+ integer j;
+ for (j = i; j < i * 2; j = j + 1)
+ num = num + 1;
+ end
+ num = num * 2;
+ end
+ operation = num;
+ end
+ endfunction
+
+ localparam res = operation(4);
+ output wire [31:0] out;
+ assign out = res;
+endmodule
diff --git a/tests/various/const_func_block_var.ys b/tests/various/const_func_block_var.ys
new file mode 100644
index 000000000..7c2e85c64
--- /dev/null
+++ b/tests/various/const_func_block_var.ys
@@ -0,0 +1 @@
+read_verilog const_func_block_var.v
diff --git a/tests/various/equiv_opt_undef.ys b/tests/various/equiv_opt_undef.ys
new file mode 100644
index 000000000..5d2c60d0a
--- /dev/null
+++ b/tests/various/equiv_opt_undef.ys
@@ -0,0 +1,35 @@
+read_ilang << EOT
+
+module \top
+ wire $a
+ wire $b
+ wire input 1 \D
+ wire input 2 \EN
+ wire output 3 \Q
+ cell $mux $x
+ parameter \WIDTH 1
+ connect \A \Q
+ connect \B \D
+ connect \S \EN
+ connect \Y $a
+ end
+ cell $ff $y
+ parameter \WIDTH 1
+ connect \D $a
+ connect \Q $b
+ end
+ cell $and $z
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $b
+ connect \B 1'x
+ connect \Y \Q
+ end
+end
+
+EOT
+
+equiv_opt -assert -undef ls
diff --git a/tests/various/integer_range_bad_syntax.ys b/tests/various/integer_range_bad_syntax.ys
new file mode 100644
index 000000000..4f427211f
--- /dev/null
+++ b/tests/various/integer_range_bad_syntax.ys
@@ -0,0 +1,6 @@
+logger -expect error "syntax error, unexpected" 1
+read_verilog -sv <<EOT
+module test_integer_range();
+parameter integer [31:0] a = 0;
+endmodule
+EOT
diff --git a/tests/various/integer_real_bad_syntax.ys b/tests/various/integer_real_bad_syntax.ys
new file mode 100644
index 000000000..942d8de77
--- /dev/null
+++ b/tests/various/integer_real_bad_syntax.ys
@@ -0,0 +1,6 @@
+logger -expect error "syntax error, unexpected TOK_REAL" 1
+read_verilog -sv <<EOT
+module test_integer_real();
+parameter integer real a = 0;
+endmodule
+EOT
diff --git a/tests/various/logic_param_simple.ys b/tests/various/logic_param_simple.ys
new file mode 100644
index 000000000..968564080
--- /dev/null
+++ b/tests/various/logic_param_simple.ys
@@ -0,0 +1,9 @@
+read_verilog -sv <<EOT
+module test_logic_param();
+parameter logic a = 0;
+parameter logic [31:0] e = 0;
+parameter logic signed b = 0;
+parameter logic unsigned c = 0;
+parameter logic unsigned [31:0] d = 0;
+endmodule
+EOT
diff --git a/tests/various/plugin.cc b/tests/various/plugin.cc
index be305fbda..451484c50 100644
--- a/tests/various/plugin.cc
+++ b/tests/various/plugin.cc
@@ -4,7 +4,7 @@ YOSYS_NAMESPACE_BEGIN
struct TestPass : public Pass {
TestPass() : Pass("test", "test") { }
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx = 1;
extra_args(args, argidx, design);
diff --git a/tests/various/signed.ys b/tests/various/signed.ys
new file mode 100644
index 000000000..2319a5da1
--- /dev/null
+++ b/tests/various/signed.ys
@@ -0,0 +1,28 @@
+# SV LRM A2.2.1
+
+read_verilog -sv <<EOT
+module test_signed();
+parameter integer signed a = 0;
+parameter integer unsigned b = 0;
+
+endmodule
+EOT
+
+design -reset
+read_verilog -sv <<EOT
+module test_signed();
+parameter logic signed [7:0] a = 0;
+parameter logic unsigned [7:0] b = 0;
+
+endmodule
+EOT
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_INTEGER" 1
+read_verilog -sv <<EOT
+module test_signed();
+parameter signed integer a = 0;
+parameter unsigned integer b = 0;
+
+endmodule
+EOT
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-26 06:19:43 +0000