diff options
Diffstat (limited to 'tests/various')
26 files changed, 407 insertions, 24 deletions
diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 4b286fd61..12d4e5048 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -3,3 +3,4 @@ /write_gzip.v /write_gzip.v.gz /run-test.mk +/plugin.so diff --git a/tests/various/bug1480.ys b/tests/various/bug1480.ys deleted file mode 100644 index 84faea08a..000000000 --- a/tests/various/bug1480.ys +++ /dev/null @@ -1,18 +0,0 @@ -read_verilog << EOF -module top(...); - -input signed [17:0] A; -input signed [17:0] B; -output X; -output Y; - -wire [35:0] P; -assign P = A * B; - -assign X = P[0]; -assign Y = P[35]; - -endmodule -EOF - -synth_xilinx diff --git a/tests/various/bug1614.ys b/tests/various/bug1614.ys new file mode 100644 index 000000000..6fbe84a4c --- /dev/null +++ b/tests/various/bug1614.ys @@ -0,0 +1,5 @@ +read_verilog <<EOT +module testcase; + wire [3:0] #1 a = 4'b0000; +endmodule +EOT diff --git a/tests/various/bug1710.ys b/tests/various/bug1710.ys new file mode 100644 index 000000000..c2ecf3c90 --- /dev/null +++ b/tests/various/bug1710.ys @@ -0,0 +1,30 @@ +logger -werror "out of bounds" +read_verilog <<EOT +module Example; + + parameter FLAG = 1; + wire [3:0] inp; + + reg out1; + initial out1 = FLAG ? &inp[2:0] : &inp[4:0]; + + reg out2; + initial + if (FLAG) + out2 = &inp[2:0]; + else + out2 = &inp[4:0]; + + wire out3; + assign out3 = FLAG ? &inp[2:0] : &inp[4:0]; + + wire out4; + generate + if (FLAG) + assign out4 = &inp[2:0]; + else + assign out4 = &inp[4:0]; + endgenerate + +endmodule +EOT diff --git a/tests/various/bug1745.ys b/tests/various/bug1745.ys new file mode 100644 index 000000000..2e5b8c2d4 --- /dev/null +++ b/tests/various/bug1745.ys @@ -0,0 +1,8 @@ +logger -expect error "syntax error, unexpected TOK_CONSTVAL" 1 +read_verilog <<EOT +module inverter(input a, output y); + + assign y = (a == 1'b0? 1'b1 : 1'b0); + +endmodule // inverter +EOT diff --git a/tests/various/bug1781.ys b/tests/various/bug1781.ys new file mode 100644 index 000000000..60dcc0830 --- /dev/null +++ b/tests/various/bug1781.ys @@ -0,0 +1,33 @@ +read_verilog <<EOT + +module top(input clk, input rst); + +reg [1:0] state; + +always @(posedge clk, posedge rst) begin + if (rst) + state <= 0; + else + case (state) + 2'b00: state <= 2'b01; + 2'b01: state <= 2'b10; + 2'b10: state <= 2'b00; + endcase +end + +sub sub_i(.i(state == 0)); + +endmodule + + +(* blackbox, keep *) +module sub(input i); +endmodule + +EOT + +proc +fsm + +# Make sure there is a driver +select -assert-any t:sub %ci %a w:* %i %ci c:* %i diff --git a/tests/various/constcomment.ys b/tests/various/constcomment.ys new file mode 100644 index 000000000..f4f2e75d8 --- /dev/null +++ b/tests/various/constcomment.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module top1; + localparam a = 8 /*foo*/ 'h ab; + localparam b = 8 'h /*foo*/ cd; + generate + if (a != 8'b10101011) $error("a incorrect!"); + if (b != 8'b11001101) $error("b incorrect!"); + endgenerate +endmodule +EOT +logger -expect error "syntax error, unexpected TOK_BASE" 1 +read_verilog <<EOT +module top2; + localparam a = 12'h4 /*foo*/'b0; +endmodule +EOT diff --git a/tests/various/deminout_unused.ys b/tests/various/deminout_unused.ys new file mode 100644 index 000000000..5ed00509d --- /dev/null +++ b/tests/various/deminout_unused.ys @@ -0,0 +1,14 @@ +read_verilog <<EOT +module top(input clk, inout [7:0] x); + +reg [3:0] ctr; +always @(posedge clk) ctr <= ctr + 1'b1; + +assign x[7:4] = ctr; +endmodule +EOT +proc +tribuf +deminout +select -assert-count 1 i:x o:x %i + diff --git a/tests/various/exec.ys b/tests/various/exec.ys new file mode 100644 index 000000000..0eec00719 --- /dev/null +++ b/tests/various/exec.ys @@ -0,0 +1,6 @@ +exec -expect-return 0 -- exit 0 +exec -expect-return 27 -- exit 27 +exec -expect-stdout nana -expect-stdout api -not-expect-stdout giraffe -- echo "bananapie" + +logger -expect error "stdout did have a line" 1 +exec -not-expect-stdout giraffe -- echo "giraffe" diff --git a/tests/various/ice40_mince_abc9.ys b/tests/various/ice40_mince_abc9.ys new file mode 100644 index 000000000..408e16f05 --- /dev/null +++ b/tests/various/ice40_mince_abc9.ys @@ -0,0 +1,17 @@ +read_verilog <<EOT + +module top(input clk, ce, input [2:0] a, b, output reg [2:0] q); + + reg [2:0] aa, bb; + + always @(posedge clk) begin + if (ce) begin + aa <= a; + end + bb <= b; + q <= aa + bb; + end +endmodule +EOT + +synth_ice40 -abc9 -dffe_min_ce_use 4 diff --git a/tests/various/logger_error.ys b/tests/various/logger_error.ys new file mode 100644 index 000000000..46fe7f506 --- /dev/null +++ b/tests/various/logger_error.ys @@ -0,0 +1,6 @@ +logger -werror "is implicitly declared." -expect error "is implicitly declared." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_nowarning.ys b/tests/various/logger_nowarning.ys new file mode 100644 index 000000000..87cbbc644 --- /dev/null +++ b/tests/various/logger_nowarning.ys @@ -0,0 +1,6 @@ +logger -expect-no-warnings -nowarn "is implicitly declared." +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warn.ys b/tests/various/logger_warn.ys new file mode 100644 index 000000000..2316ae4c6 --- /dev/null +++ b/tests/various/logger_warn.ys @@ -0,0 +1,6 @@ +logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/logger_warning.ys b/tests/various/logger_warning.ys new file mode 100644 index 000000000..642b1b97b --- /dev/null +++ b/tests/various/logger_warning.ys @@ -0,0 +1,6 @@ +logger -expect warning "is implicitly declared." 2 +read_verilog << EOF +module top(...); + assign b = w; +endmodule +EOF diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys index 85d6267c5..ba94787bc 100644 --- a/tests/various/mem2reg.ys +++ b/tests/various/mem2reg.ys @@ -9,6 +9,6 @@ EOT proc cd top -select -assert-count 1 m:data1 a:src=<<EOT:4 %i -select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i +select -assert-count 1 m:data1 a:src=<<EOT:4.43-4.48 %i +select -assert-count 2 w:data2[*] a:src=<<EOT:5.41-5.46 %i select -assert-none a:mem2reg diff --git a/tests/various/plugin.cc b/tests/various/plugin.cc new file mode 100644 index 000000000..be305fbda --- /dev/null +++ b/tests/various/plugin.cc @@ -0,0 +1,15 @@ +#include "kernel/rtlil.h" + +YOSYS_NAMESPACE_BEGIN + +struct TestPass : public Pass { + TestPass() : Pass("test", "test") { } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + { + size_t argidx = 1; + extra_args(args, argidx, design); + log("Plugin test passed!\n"); + } +} TestPass; + +YOSYS_NAMESPACE_END diff --git a/tests/various/plugin.sh b/tests/various/plugin.sh new file mode 100644 index 000000000..d6d4aee59 --- /dev/null +++ b/tests/various/plugin.sh @@ -0,0 +1,6 @@ +set -e +rm -f plugin.so +CXXFLAGS=$(../../yosys-config --cxxflags) +CXXFLAGS=${CXXFLAGS// -I\/usr\/local\/share\/yosys\/include/ -I..\/..\/share\/include} +../../yosys-config --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc +../../yosys -m ./plugin.so -p "test" | grep -q "Plugin test passed!" diff --git a/tests/various/pmux2shiftx.v b/tests/various/pmux2shiftx.v index 563394080..c1994e92c 100644 --- a/tests/various/pmux2shiftx.v +++ b/tests/various/pmux2shiftx.v @@ -33,7 +33,7 @@ module pmux2shiftx_test ( end endmodule -module issue01135(input [7:0] i, output o); +module issue01135(input [7:0] i, output reg o); always @* case (i[6:3]) 4: o <= i[0]; diff --git a/tests/various/specify.v b/tests/various/specify.v index 5d44d78f7..c160d2ec4 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -7,11 +7,9 @@ module test ( if (EN) Q <= D; specify -`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); -`endif endspecify endmodule @@ -37,3 +35,30 @@ specify (posedge clk *> (q +: d)) = (3,1); endspecify endmodule + +module test3(input clk, input [1:0] d, output [1:0] q); +specify + (posedge clk => (q +: d)) = (3,1); + (posedge clk *> (q +: d)) = (3,1); +endspecify +endmodule + +module test4(input clk, d, output q); +specify + $setup(d, posedge clk, 1:2:3); + $setuphold(d, posedge clk, 1:2:3, 4:5:6); +endspecify +endmodule + +module test5(input clk, d, e, output q); +specify + $setup(d, posedge clk &&& e, 1:2:3); +endspecify +endmodule + +module test6(input clk, d, e, output q); +specify + (d[0] *> q[0]) = (3,1); + (posedge clk[0] => (q[0] +: d[0])) = (3,1); +endspecify +endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index 00597e1e2..9d55b8eb5 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -55,4 +55,23 @@ equiv_induct -seq 5 equiv_status -assert design -reset -read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v +read_verilog -specify <<EOT +(* blackbox *) +module test7_sub(input i, output o); +specify + (i => o) = 1; +endspecify +assign o = ~i; +endmodule + +module test7(input i, output o); + wire w; + test7_sub unused(i, w); + test7_sub used(i, o); +endmodule +EOT +hierarchy +cd test7 +clean +select -assert-count 1 c:used +select -assert-none c:* c:used %d diff --git a/tests/various/src.ys b/tests/various/src.ys new file mode 100644 index 000000000..89d6700ca --- /dev/null +++ b/tests/various/src.ys @@ -0,0 +1,8 @@ +logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1 +logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1 +read_verilog <<EOT +module top(input i, output o, p); +always @* o <= i; +always @* p = i; +endmodule +EOT diff --git a/tests/various/submod.ys b/tests/various/submod.ys new file mode 100644 index 000000000..4fb45043b --- /dev/null +++ b/tests/various/submod.ys @@ -0,0 +1,124 @@ +read_verilog <<EOT +module top(input a, output b); +wire c; +(* submod="bar" *) sub s1(a, c); +assign b = c; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +check -assert +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] b); +(* submod="bar" *) sub s1(a, b[1]); +assign b[0] = 1'b0; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +check -assert top +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] b, c); +(* submod="bar" *) sub s1(a, b[0]); +(* submod="bar" *) sub s2(a, c[1]); +assign c = b; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +check -assert top +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog <<EOT +module top(input d, c, (* init = 3'b011 *) output reg [2:0] q); +(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1])); +DFF s2(.D(d), .C(c), .Q(q[0])); +DFF s3(.D(d), .C(c), .Q(q[2])); +endmodule + +module DFF(input D, C, output Q); +parameter INIT = 1'b0; +endmodule +EOT + +hierarchy -top top +proc + +submod +dffinit -ff DFF Q INIT +check -noinit -assert + + +design -reset +read_verilog <<EOT +module top(input d, c, output reg [2:0] q); +(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1])); +DFF s2(.D(d), .C(c), .Q(q[0])); +DFF s3(.D(d), .C(c), .Q(q[2])); +endmodule +EOT + +hierarchy -top top +proc + +submod +flatten + +read_verilog <<EOT +module DFF(input D, C, output Q); +endmodule +EOT + +check -assert diff --git a/tests/various/sv_defines.ys b/tests/various/sv_defines.ys new file mode 100644 index 000000000..8e70ee0ee --- /dev/null +++ b/tests/various/sv_defines.ys @@ -0,0 +1,33 @@ +# Check that basic macro expansions do what you'd expect + +read_verilog <<EOT +`define empty_arglist() 123 +`define one_arg(x) 123+x +`define opt_arg(x = 1) 123+x +`define two_args(x, y = (1+23)) x+y +`define nested_comma(x = {31'b0, 1'b1}, y=3) x+y + +module top; + localparam a = `empty_arglist(); + localparam b = `one_arg(10); + localparam c = `opt_arg(10); + localparam d = `opt_arg(); + localparam e = `two_args(1,2); + localparam f = `two_args(1); + localparam g = `nested_comma(1, 2); + localparam h = `nested_comma({31'b0, (1'b0)}); + localparam i = `nested_comma(, 1); + + generate + if (a != 123) $error("a bad"); + if (b != 133) $error("b bad"); + if (c != 133) $error("c bad"); + if (d != 124) $error("d bad"); + if (e != 3) $error("e bad"); + if (f != 25) $error("f bad"); + if (g != 3) $error("g bad"); + if (h != 3) $error("h bad"); + if (i != 2) $error("i bad"); + endgenerate +endmodule +EOT diff --git a/tests/various/sv_defines_dup.ys b/tests/various/sv_defines_dup.ys new file mode 100644 index 000000000..38418ba8f --- /dev/null +++ b/tests/various/sv_defines_dup.ys @@ -0,0 +1,5 @@ +# Check for duplicate arguments +logger -expect error "Duplicate macro arguments with name `x'" 1 +read_verilog <<EOT +`define duplicate_arg(x, x) +EOT diff --git a/tests/various/sv_defines_mismatch.ys b/tests/various/sv_defines_mismatch.ys new file mode 100644 index 000000000..ab6e899de --- /dev/null +++ b/tests/various/sv_defines_mismatch.ys @@ -0,0 +1,5 @@ +# Check that we spot mismatched brackets +logger -expect error "Mismatched brackets in macro argument: \[ and }." 1 +read_verilog <<EOT +`define foo(x=[1,2}) +EOT diff --git a/tests/various/sv_defines_too_few.ys b/tests/various/sv_defines_too_few.ys new file mode 100644 index 000000000..295884809 --- /dev/null +++ b/tests/various/sv_defines_too_few.ys @@ -0,0 +1,7 @@ +# Check that we don't allow passing too few arguments (and, while we're at it, check that passing "no" +# arguments actually passes 1 empty argument). +logger -expect error "Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\)." 1 +read_verilog <<EOT +`define foo(x=1, y) +`foo() +EOT |