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-rw-r--r--tests/various/.gitignore1
-rw-r--r--tests/various/const_arg_loop.v29
-rw-r--r--tests/various/fib.v65
-rw-r--r--tests/various/fib.ys6
-rw-r--r--tests/various/func_port_implied_dir.sv23
-rw-r--r--tests/various/func_port_implied_dir.ys6
-rw-r--r--tests/various/gen_if_null.v12
-rw-r--r--tests/various/gen_if_null.ys4
-rw-r--r--tests/various/memory_word_as_index.data4
-rw-r--r--tests/various/memory_word_as_index.v21
-rw-r--r--tests/various/memory_word_as_index.ys23
-rw-r--r--tests/various/port_sign_extend.v95
-rw-r--r--tests/various/port_sign_extend.ys29
-rw-r--r--tests/various/rand_const.sv8
-rw-r--r--tests/various/rand_const.ys1
15 files changed, 321 insertions, 6 deletions
diff --git a/tests/various/.gitignore b/tests/various/.gitignore
index 12d4e5048..2bb6c7179 100644
--- a/tests/various/.gitignore
+++ b/tests/various/.gitignore
@@ -4,3 +4,4 @@
/write_gzip.v.gz
/run-test.mk
/plugin.so
+/plugin.so.dSYM
diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v
index 3bfff4acd..358fb439a 100644
--- a/tests/various/const_arg_loop.v
+++ b/tests/various/const_arg_loop.v
@@ -14,6 +14,11 @@ module top;
end
endfunction
+ function automatic [31:0] pass_through;
+ input [31:0] inp;
+ pass_through = inp;
+ endfunction
+
function automatic [31:0] operation2;
input [4:0] var;
input integer num;
@@ -39,6 +44,18 @@ module top;
end
endfunction
+ function automatic [16:0] operation4;
+ input [15:0] a;
+ input b;
+ operation4 = {a, b};
+ endfunction
+
+ function automatic integer operation5;
+ input x;
+ integer x;
+ operation5 = x;
+ endfunction
+
wire [31:0] a;
assign a = 2;
@@ -47,18 +64,30 @@ module top;
wire [31:0] x1;
assign x1 = operation1(A, a);
+ wire [31:0] x1b;
+ assign x1b = operation1(pass_through(A), a);
+
wire [31:0] x2;
assign x2 = operation2(A, a);
wire [31:0] x3;
assign x3 = operation3(A, a);
+ wire [16:0] x4;
+ assign x4 = operation4(a[15:0], 0);
+
+ wire [31:0] x5;
+ assign x5 = operation5(64);
+
// `define VERIFY
`ifdef VERIFY
assert property (a == 2);
assert property (A == 3);
assert property (x1 == 16);
+ assert property (x1b == 16);
assert property (x2 == 4);
assert property (x3 == 16);
+ assert property (x4 == a << 1);
+ assert property (x5 == 64);
`endif
endmodule
diff --git a/tests/various/fib.v b/tests/various/fib.v
new file mode 100644
index 000000000..986749626
--- /dev/null
+++ b/tests/various/fib.v
@@ -0,0 +1,65 @@
+module gate(
+ off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9
+);
+ input wire signed [31:0] off;
+
+ function automatic integer fib(
+ input integer k
+ );
+ if (k == 0)
+ fib = 0;
+ else if (k == 1)
+ fib = 1;
+ else
+ fib = fib(k - 1) + fib(k - 2);
+ endfunction
+
+ function automatic integer fib_wrap(
+ input integer k,
+ output integer o
+ );
+ o = off + fib(k);
+ endfunction
+
+ output integer fib0;
+ output integer fib1;
+ output integer fib2;
+ output integer fib3;
+ output integer fib4;
+ output integer fib5;
+ output integer fib6;
+ output integer fib7;
+ output integer fib8;
+ output integer fib9;
+
+ initial begin : blk
+ integer unused;
+ unused = fib_wrap(0, fib0);
+ unused = fib_wrap(1, fib1);
+ unused = fib_wrap(2, fib2);
+ unused = fib_wrap(3, fib3);
+ unused = fib_wrap(4, fib4);
+ unused = fib_wrap(5, fib5);
+ unused = fib_wrap(6, fib6);
+ unused = fib_wrap(7, fib7);
+ unused = fib_wrap(8, fib8);
+ unused = fib_wrap(9, fib9);
+ end
+endmodule
+
+module gold(
+ off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9
+);
+ input wire signed [31:0] off;
+
+ output integer fib0 = off + 0;
+ output integer fib1 = off + 1;
+ output integer fib2 = off + 1;
+ output integer fib3 = off + 2;
+ output integer fib4 = off + 3;
+ output integer fib5 = off + 5;
+ output integer fib6 = off + 8;
+ output integer fib7 = off + 13;
+ output integer fib8 = off + 21;
+ output integer fib9 = off + 34;
+endmodule
diff --git a/tests/various/fib.ys b/tests/various/fib.ys
new file mode 100644
index 000000000..946e0738a
--- /dev/null
+++ b/tests/various/fib.ys
@@ -0,0 +1,6 @@
+read_verilog fib.v
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/various/func_port_implied_dir.sv b/tests/various/func_port_implied_dir.sv
new file mode 100644
index 000000000..0424f1b46
--- /dev/null
+++ b/tests/various/func_port_implied_dir.sv
@@ -0,0 +1,23 @@
+module gate(w, x, y, z);
+ function automatic integer bar(
+ integer a
+ );
+ bar = 2 ** a;
+ endfunction
+ output integer w = bar(4);
+
+ function automatic integer foo(
+ input integer a, /* implicitly input */ integer b,
+ output integer c, /* implicitly output */ integer d
+ );
+ c = 42;
+ d = 51;
+ foo = a + b + 1;
+ endfunction
+ output integer x, y, z;
+ initial x = foo(1, 2, y, z);
+endmodule
+
+module gold(w, x, y, z);
+ output integer w = 16, x = 4, y = 42, z = 51;
+endmodule
diff --git a/tests/various/func_port_implied_dir.ys b/tests/various/func_port_implied_dir.ys
new file mode 100644
index 000000000..b5c22a05b
--- /dev/null
+++ b/tests/various/func_port_implied_dir.ys
@@ -0,0 +1,6 @@
+read_verilog -sv func_port_implied_dir.sv
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/various/gen_if_null.v b/tests/various/gen_if_null.v
index a12ac6288..992bc68b3 100644
--- a/tests/various/gen_if_null.v
+++ b/tests/various/gen_if_null.v
@@ -1,13 +1,17 @@
-module test(x, y, z);
+`default_nettype none
+module test;
localparam OFF = 0;
generate
if (OFF) ;
- else input x;
- if (!OFF) input y;
+ else wire x;
+ if (!OFF) wire y;
else ;
if (OFF) ;
else ;
if (OFF) ;
- input z;
+ wire z;
endgenerate
+ assign genblk1.x = 0;
+ assign genblk2.y = 0;
+ assign z = 0;
endmodule
diff --git a/tests/various/gen_if_null.ys b/tests/various/gen_if_null.ys
index 31dfc444b..0733e3a94 100644
--- a/tests/various/gen_if_null.ys
+++ b/tests/various/gen_if_null.ys
@@ -1,4 +1,4 @@
read_verilog gen_if_null.v
-select -assert-count 1 test/x
-select -assert-count 1 test/y
+select -assert-count 1 test/genblk1.x
+select -assert-count 1 test/genblk2.y
select -assert-count 1 test/z
diff --git a/tests/various/memory_word_as_index.data b/tests/various/memory_word_as_index.data
new file mode 100644
index 000000000..d525c18ee
--- /dev/null
+++ b/tests/various/memory_word_as_index.data
@@ -0,0 +1,4 @@
+00 04 08 0c
+10 14 18 1c
+20 24 28 2c
+30 34 38 3c
diff --git a/tests/various/memory_word_as_index.v b/tests/various/memory_word_as_index.v
new file mode 100644
index 000000000..a99ea9566
--- /dev/null
+++ b/tests/various/memory_word_as_index.v
@@ -0,0 +1,21 @@
+`define DATA 64'h492e5c4d7747e032
+
+`define GATE(n, expr) \
+module gate``n(sel, out); \
+ input wire [3:0] sel; \
+ output wire out; \
+ reg [63:0] bits; \
+ reg [5:0] ptrs[15:0]; \
+ initial bits = `DATA; \
+ initial $readmemh("memory_word_as_index.data", ptrs); \
+ assign out = expr; \
+endmodule
+
+`GATE(1, bits[ptrs[sel]])
+`GATE(2, bits[ptrs[sel][5:0]])
+`GATE(3, bits[ptrs[sel]+:1])
+
+module gold(sel, out);
+ input wire [3:0] sel;
+ output wire out = `DATA >> (sel * 4);
+endmodule
diff --git a/tests/various/memory_word_as_index.ys b/tests/various/memory_word_as_index.ys
new file mode 100644
index 000000000..9a2dea40e
--- /dev/null
+++ b/tests/various/memory_word_as_index.ys
@@ -0,0 +1,23 @@
+read_verilog memory_word_as_index.v
+
+hierarchy
+proc
+memory
+flatten
+opt -full
+
+equiv_make gold gate1 equiv
+equiv_simple
+equiv_status -assert
+
+delete equiv
+
+equiv_make gold gate2 equiv
+equiv_simple
+equiv_status -assert
+
+delete equiv
+
+equiv_make gold gate3 equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/various/port_sign_extend.v b/tests/various/port_sign_extend.v
new file mode 100644
index 000000000..813ceb503
--- /dev/null
+++ b/tests/various/port_sign_extend.v
@@ -0,0 +1,95 @@
+module GeneratorSigned1(out);
+ output wire signed out;
+ assign out = 1;
+endmodule
+
+module GeneratorUnsigned1(out);
+ output wire out;
+ assign out = 1;
+endmodule
+
+module GeneratorSigned2(out);
+ output wire signed [1:0] out;
+ assign out = 2;
+endmodule
+
+module GeneratorUnsigned2(out);
+ output wire [1:0] out;
+ assign out = 2;
+endmodule
+
+module PassThrough(a, b);
+ input wire [3:0] a;
+ output wire [3:0] b;
+ assign b = a;
+endmodule
+
+module act(o1, o2, o3, o4, o5, o6, o7, o8, o9, yay1, nay1, yay2, nay2);
+ output wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8, o9;
+
+ // unsigned constant
+ PassThrough pt1(1'b1, o1);
+
+ // unsigned wire
+ wire tmp2;
+ assign tmp2 = 1'sb1;
+ PassThrough pt2(tmp2, o2);
+
+ // signed constant
+ PassThrough pt3(1'sb1, o3);
+
+ // signed wire
+ wire signed tmp4;
+ assign tmp4 = 1'sb1;
+ PassThrough pt4(tmp4, o4);
+
+ // signed expressions
+ wire signed [1:0] tmp5a = 2'b11;
+ wire signed [1:0] tmp5b = 2'b01;
+ PassThrough pt5(tmp5a ^ tmp5b, o5);
+
+ wire signed [2:0] tmp6a = 3'b100;
+ wire signed [2:0] tmp6b = 3'b001;
+ PassThrough pt6(tmp6a ? tmp6a : tmp6b, o6);
+
+ wire signed [2:0] tmp7 = 3'b011;
+ PassThrough pt7(~tmp7, o7);
+
+ reg signed [2:0] tmp8 [0:0];
+ initial tmp8[0] = 3'b101;
+ PassThrough pt8(tmp8[0], o8);
+
+ wire signed [2:0] tmp9a = 3'b100;
+ wire signed [1:0] tmp9b = 2'b11;
+ PassThrough pt9(0 ? tmp9a : tmp9b, o9);
+
+ output wire [2:0] yay1, nay1;
+ GeneratorSigned1 os1(yay1);
+ GeneratorUnsigned1 ou1(nay1);
+
+ output wire [2:0] yay2, nay2;
+ GeneratorSigned2 os2(yay2);
+ GeneratorUnsigned2 ou2(nay2);
+endmodule
+
+module ref(o1, o2, o3, o4, o5, o6, o7, o8, o9, yay1, nay1, yay2, nay2);
+ output wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8, o9;
+
+ assign o1 = 4'b0001;
+ assign o2 = 4'b0001;
+ assign o3 = 4'b1111;
+ assign o4 = 4'b1111;
+ assign o5 = 4'b1110;
+ assign o6 = 4'b1100;
+ assign o7 = 4'b1100;
+ assign o8 = 4'b1101;
+ assign o9 = 4'b1111;
+
+ output wire [2:0] yay1, nay1;
+ assign yay1 = 3'b111;
+ assign nay1 = 3'b001;
+
+ output wire [2:0] yay2, nay2;
+ assign yay2 = 3'b110;
+ assign nay2 = 3'b010;
+endmodule
diff --git a/tests/various/port_sign_extend.ys b/tests/various/port_sign_extend.ys
new file mode 100644
index 000000000..6d1adf7f3
--- /dev/null
+++ b/tests/various/port_sign_extend.ys
@@ -0,0 +1,29 @@
+read_verilog -nomem2reg port_sign_extend.v
+hierarchy
+flatten
+proc
+memory
+equiv_make ref act equiv
+equiv_simple
+equiv_status -assert
+
+delete
+
+read_verilog -nomem2reg port_sign_extend.v
+flatten
+proc
+memory
+equiv_make ref act equiv
+equiv_simple
+equiv_status -assert
+
+delete
+
+read_verilog -nomem2reg port_sign_extend.v
+hierarchy
+proc
+memory
+equiv_make ref act equiv
+prep -flatten -top equiv
+equiv_induct
+equiv_status -assert
diff --git a/tests/various/rand_const.sv b/tests/various/rand_const.sv
new file mode 100644
index 000000000..be00812c0
--- /dev/null
+++ b/tests/various/rand_const.sv
@@ -0,0 +1,8 @@
+module top;
+ rand const reg rx;
+ const reg ry;
+ rand reg rz;
+ rand const integer ix;
+ const integer iy;
+ rand integer iz;
+endmodule
diff --git a/tests/various/rand_const.ys b/tests/various/rand_const.ys
new file mode 100644
index 000000000..74e43c7cc
--- /dev/null
+++ b/tests/various/rand_const.ys
@@ -0,0 +1 @@
+read_verilog -sv rand_const.sv
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 11:43:03 +0000