7 files changed, 56 insertions, 0 deletions
diff --git a/tests/various/bug1745.ys b/tests/various/bug1745.ys
new file mode 100644
index 000000000..2e5b8c2d4
--- /dev/null
+++ b/tests/various/bug1745.ys
@@ -0,0 +1,8 @@
+logger -expect error "syntax error, unexpected TOK_CONSTVAL" 1
+read_verilog <<EOT
+module inverter(input a, output y);
+
+   assign y = (a == 1'b0? 1'b1 : 1'b0);
+   
+endmodule // inverter
+EOT
diff --git a/tests/various/constcomment.ys b/tests/various/constcomment.ys
new file mode 100644
index 000000000..f4f2e75d8
--- /dev/null
+++ b/tests/various/constcomment.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module top1;
+        localparam a = 8 /*foo*/ 'h ab;
+        localparam b = 8 'h /*foo*/ cd;
+        generate
+                if (a != 8'b10101011) $error("a incorrect!");
+                if (b != 8'b11001101) $error("b incorrect!");
+        endgenerate
+endmodule
+EOT
+logger -expect error "syntax error, unexpected TOK_BASE" 1
+read_verilog <<EOT
+module top2;
+	localparam a = 12'h4 /*foo*/'b0;
+endmodule
+EOT
diff --git a/tests/various/logger_error.ys b/tests/various/logger_error.ys
new file mode 100644
index 000000000..46fe7f506
--- /dev/null
+++ b/tests/various/logger_error.ys
@@ -0,0 +1,6 @@
+logger -werror "is implicitly declared." -expect error "is implicitly declared." 1
+read_verilog << EOF
+module top(...);
+	assign b = w;
+endmodule
+EOF
diff --git a/tests/various/logger_nowarning.ys b/tests/various/logger_nowarning.ys
new file mode 100644
index 000000000..87cbbc644
--- /dev/null
+++ b/tests/various/logger_nowarning.ys
@@ -0,0 +1,6 @@
+logger -expect-no-warnings -nowarn "is implicitly declared."
+read_verilog << EOF
+module top(...);
+	assign b = w;
+endmodule
+EOF
diff --git a/tests/various/logger_warn.ys b/tests/various/logger_warn.ys
new file mode 100644
index 000000000..2316ae4c6
--- /dev/null
+++ b/tests/various/logger_warn.ys
@@ -0,0 +1,6 @@
+logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1
+read_verilog << EOF
+module top(...);
+	assign b = w;
+endmodule
+EOF
diff --git a/tests/various/logger_warning.ys b/tests/various/logger_warning.ys
new file mode 100644
index 000000000..642b1b97b
--- /dev/null
+++ b/tests/various/logger_warning.ys
@@ -0,0 +1,6 @@
+logger -expect warning "is implicitly declared." 2
+read_verilog << EOF
+module top(...);
+	assign b = w;
+endmodule
+EOF
diff --git a/tests/various/src.ys b/tests/various/src.ys
new file mode 100644
index 000000000..89d6700ca
--- /dev/null
+++ b/tests/various/src.ys
@@ -0,0 +1,8 @@
+logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1
+logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1
+read_verilog <<EOT
+module top(input i, output o, p);
+always @* o <= i;
+always @* p = i;
+endmodule
+EOT