4 files changed, 0 insertions, 94 deletions
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index f1bd5ea8e..7c189fff8 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -110,29 +110,3 @@ always @* begin
     endcase
 end
 endmodule
-
-module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
-always @*
-    if (s[0] == 1'b0)
-     if (s[1] == 1'b0)
-      if (s[2] == 1'b0)
-       o <= i[0*W+:W];
-      else
-       o <= i[1*W+:W];
-     else
-      if (s[2] == 1'b0)
-       o <= i[2*W+:W];
-      else
-       o <= i[3*W+:W];
-    else
-     if (s[1] == 1'b0)
-      if (s[2] == 1'b0)
-       o <= i[4*W+:W];
-      else
-       o <= i[5*W+:W];
-     else
-      if (s[2] == 1'b0)
-       o <= i[6*W+:W];
-      else
-       o <= i[7*W+:W];
-endmodule
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 9ea743b9f..0c5b82818 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -133,18 +133,3 @@ design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
-
-design -load read
-hierarchy -top mux_if_bal_8_2
-prep
-design -save gold
-muxpack
-opt
-stat
-select -assert-count 7 t:$mux
-select -assert-count 0 t:$pmux
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
deleted file mode 100644
index 56e05c2c0..000000000
--- a/tests/various/shregmap.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module shregmap_test(input i, clk, output [1:0] q);
-reg head = 1'b0;
-reg [3:0] shift1 = 4'b0000;
-reg [3:0] shift2 = 4'b0000;
-
-always @(posedge clk) begin
-    head <= i;
-    shift1 <= {shift1[2:0], head};
-    shift2 <= {shift2[2:0], head};
-end
-
-assign q = {shift2[3], shift1[3]};
-endmodule
-
-module $__SHREG_DFF_P_(input C, D, output Q);
-parameter DEPTH = 1;
-parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
-reg [DEPTH-1:0] r = INIT;
-always @(posedge C) 
-    r <= { r[DEPTH-2:0], D };
-assign Q = r[DEPTH-1];
-endmodule
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
deleted file mode 100644
index ca7f47015..000000000
--- a/tests/various/shregmap.ys
+++ /dev/null
@@ -1,31 +0,0 @@
-read_verilog shregmap.v
-design -copy-to model $__SHREG_DFF_P_
-hierarchy -top shregmap_test
-prep
-design -save gold
-
-techmap
-shregmap -init
-
-opt
-
-stat
-# show -width
-select -assert-count 1 t:$_DFF_P_
-select -assert-count 2 t:$__SHREG_DFF_P_
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_
-prep
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports -seq 5 miter
-
-design -load gold
-stat
-
-design -load gate
-stat