6 files changed, 96 insertions, 0 deletions
diff --git a/tests/various/.gitignore b/tests/various/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/various/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/tests/various/constmsk_test.v b/tests/various/constmsk_test.v
new file mode 100644
index 000000000..0d0e58fef
--- /dev/null
+++ b/tests/various/constmsk_test.v
@@ -0,0 +1,4 @@
+module test(input [3:0] A, output [3:0] Y1, Y2);
+    assign Y1 = |{A[3], 1'b0, A[1]};
+    assign Y2 = |{A[2], 1'b1, A[0]};
+endmodule
diff --git a/tests/various/constmsk_test.ys b/tests/various/constmsk_test.ys
new file mode 100644
index 000000000..ce36efc35
--- /dev/null
+++ b/tests/various/constmsk_test.ys
@@ -0,0 +1,15 @@
+read_verilog constmsk_test.v
+
+copy test gold
+rename test gate
+
+cd gate
+techmap -map constmsk_testmap.v;;
+cd ..
+
+select -assert-count 2 gold/r:A_WIDTH=3
+select -assert-count 1 gate/r:A_WIDTH=2
+select -assert-count 1 gate/c:*
+
+miter -equiv -flatten gold gate miter
+sat -verify -prove trigger 0 miter
diff --git a/tests/various/constmsk_testmap.v b/tests/various/constmsk_testmap.v
new file mode 100644
index 000000000..fab1b1bbc
--- /dev/null
+++ b/tests/various/constmsk_testmap.v
@@ -0,0 +1,49 @@
+(* techmap_celltype = "$reduce_or" *)
+module my_opt_reduce_or(...);
+    parameter A_SIGNED = 0;
+    parameter A_WIDTH = 1;
+    parameter Y_WIDTH = 1;
+
+    input [A_WIDTH-1:0] A;
+    output reg [Y_WIDTH-1:0] Y;
+
+    parameter _TECHMAP_CONSTMSK_A_ = 0;
+    parameter _TECHMAP_CONSTVAL_A_ = 0;
+
+    wire _TECHMAP_FAIL_ = count_nonconst_bits() == A_WIDTH;
+    wire [1024:0] _TECHMAP_DO_ = "proc;;";
+
+    function integer count_nonconst_bits;
+        integer i;
+        begin
+            count_nonconst_bits = 0;
+            for (i = 0; i < A_WIDTH; i=i+1)
+                if (!_TECHMAP_CONSTMSK_A_[i])
+                    count_nonconst_bits = count_nonconst_bits+1;
+        end
+    endfunction
+
+    function has_const_one;
+        integer i;
+        begin
+            has_const_one = 0;
+            for (i = 0; i < A_WIDTH; i=i+1)
+                if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'b1)
+                    has_const_one = 1;
+        end
+    endfunction
+
+    integer i;
+    reg [count_nonconst_bits()-1:0] tmp;
+
+    always @* begin
+        if (has_const_one()) begin
+            Y = 1;
+        end else begin
+            for (i = 0; i < A_WIDTH; i=i+1)
+                if (!_TECHMAP_CONSTMSK_A_[i])
+                    tmp = {A[i], tmp[count_nonconst_bits()-1:1]};
+            Y = |tmp;
+        end
+    end
+endmodule
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
new file mode 100755
index 000000000..67e1beb23
--- /dev/null
+++ b/tests/various/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+	echo "Running $x.."
+	../../yosys -ql ${x%.ys}.log $x
+done
diff --git a/tests/various/submod_extract.ys b/tests/various/submod_extract.ys
new file mode 100644
index 000000000..8d11c21d3
--- /dev/null
+++ b/tests/various/submod_extract.ys
@@ -0,0 +1,21 @@
+read_verilog << EOT
+  module test(input [7:0] a, b, c, d, output [7:0] x, y, z);
+    assign x = a + b, y = b + c, z = c + d;
+  endmodule
+EOT
+
+copy test gold
+rename test gate
+
+submod -name mycell gate/x %ci*
+design -copy-to mymap mycell
+extract -map %mymap gate
+
+select -assert-count 3 gold/t:*
+select -assert-count 3 gold/t:$add
+
+select -assert-count 3 gate/t:*
+select -assert-count 3 gate/t:mycell
+
+miter -equiv -flatten gold gate miter
+sat -verify -prove trigger 0 miter