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-rw-r--r--tests/verilog/always_comb_nolatch_5.ys15
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diff --git a/tests/verilog/always_comb_nolatch_5.ys b/tests/verilog/always_comb_nolatch_5.ys
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+++ b/tests/verilog/always_comb_nolatch_5.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOF
+module top;
+logic [4:0] x;
+logic z;
+assign z = 1'b1;
+always_comb begin : foo
+ x = '0;
+ if (z) begin : bar
+ for (int i = 0; i < 5; i++)
+ x[i] = 1'b1;
+ end
+end
+endmodule
+EOF
+proc