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Diffstat (limited to 'tests/verilog/conflict_memory_wire.ys')
| -rw-r--r-- | tests/verilog/conflict_memory_wire.ys | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/verilog/conflict_memory_wire.ys b/tests/verilog/conflict_memory_wire.ys new file mode 100644 index 000000000..5c296074f --- /dev/null +++ b/tests/verilog/conflict_memory_wire.ys @@ -0,0 +1,7 @@ +logger -expect error "Cannot add memory `\\x' because a signal with the same name was already created" 1 +read_verilog <<EOT +module top; + reg [2:0] x; + reg [2:0] x [0:0]; +endmodule +EOT |