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-rw-r--r--tests/verilog/hidden_decl.ys11
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diff --git a/tests/verilog/hidden_decl.ys b/tests/verilog/hidden_decl.ys
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+++ b/tests/verilog/hidden_decl.ys
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+logger -expect error "Identifier `\\y' is implicitly declared and `default_nettype is set to none" 1
+read_verilog <<EOT
+`default_nettype none
+module top1;
+ wire x;
+ generate
+ if (1) wire y;
+ endgenerate
+ assign x = y;
+endmodule
+EOT