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-rw-r--r--tests/verilog/mem_bounds.ys6
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/verilog/mem_bounds.ys b/tests/verilog/mem_bounds.ys
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+read_verilog -sv -mem2reg mem_bounds.sv
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef