aboutsummaryrefslogtreecommitdiffstats
path: root/tests/verilog/wire_and_var.ys
diff options
context:
space:
mode:
Diffstat (limited to 'tests/verilog/wire_and_var.ys')
-rw-r--r--tests/verilog/wire_and_var.ys9
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/verilog/wire_and_var.ys b/tests/verilog/wire_and_var.ys
new file mode 100644
index 000000000..9359a9d55
--- /dev/null
+++ b/tests/verilog/wire_and_var.ys
@@ -0,0 +1,9 @@
+logger -expect warning "wire '\\wire_1' is assigned in a block" 1
+logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1
+
+logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1
+
+logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1
+logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1
+
+read_verilog -sv wire_and_var.sv