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-rw-r--r--tests/verilog/atom_type_signedness.ys19
-rw-r--r--tests/verilog/block_labels.ys26
-rw-r--r--tests/verilog/bug2493.ys12
-rw-r--r--tests/verilog/bug656.v21
-rw-r--r--tests/verilog/bug656.ys13
-rw-r--r--tests/verilog/genblk_case.v26
-rw-r--r--tests/verilog/genblk_case.ys15
-rw-r--r--tests/verilog/genblk_port_decl.ys12
-rw-r--r--tests/verilog/hidden_decl.ys11
-rw-r--r--tests/verilog/unnamed_block.ys28
-rw-r--r--tests/verilog/unnamed_genblk.sv39
-rw-r--r--tests/verilog/unnamed_genblk.ys8
-rw-r--r--tests/verilog/wire_and_var.sv33
-rw-r--r--tests/verilog/wire_and_var.ys9
14 files changed, 272 insertions, 0 deletions
diff --git a/tests/verilog/atom_type_signedness.ys b/tests/verilog/atom_type_signedness.ys
new file mode 100644
index 000000000..22bbe6efc
--- /dev/null
+++ b/tests/verilog/atom_type_signedness.ys
@@ -0,0 +1,19 @@
+read_verilog -dump_ast1 -dump_ast2 -sv <<EOT
+module dut();
+
+enum integer { uInteger = -10 } a;
+enum int { uInt = -11 } b;
+enum shortint { uShortInt = -12 } c;
+enum byte { uByte = -13 } d;
+
+always_comb begin
+ assert(-10 == uInteger);
+ assert(-11 == uInt);
+ assert(-12 == uShortInt);
+ assert(-13 == uByte);
+end
+endmodule
+EOT
+hierarchy; proc; opt
+select -module dut
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all
diff --git a/tests/verilog/block_labels.ys b/tests/verilog/block_labels.ys
new file mode 100644
index 000000000..e76bcf771
--- /dev/null
+++ b/tests/verilog/block_labels.ys
@@ -0,0 +1,26 @@
+read_verilog <<EOT
+module foo;
+
+ genvar a = 0;
+ for (a = 0; a < 10; a++) begin : a
+ end : a
+endmodule
+EOT
+read_verilog <<EOT
+module foo2;
+
+ genvar a = 0;
+ for (a = 0; a < 10; a++) begin : a
+ end
+endmodule
+EOT
+
+logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
+read_verilog <<EOT
+module foo3;
+
+ genvar a = 0;
+ for (a = 0; a < 10; a++) begin : a
+ end : b
+endmodule
+EOT
diff --git a/tests/verilog/bug2493.ys b/tests/verilog/bug2493.ys
new file mode 100644
index 000000000..380d2a823
--- /dev/null
+++ b/tests/verilog/bug2493.ys
@@ -0,0 +1,12 @@
+logger -expect error "Failed to detect width for identifier \\genblk1\.y!" 1
+read_verilog <<EOT
+module top1;
+ wire x;
+ generate
+ if (1) begin
+ mod y();
+ assign x = y;
+ end
+ endgenerate
+endmodule
+EOT
diff --git a/tests/verilog/bug656.v b/tests/verilog/bug656.v
new file mode 100644
index 000000000..068d045fd
--- /dev/null
+++ b/tests/verilog/bug656.v
@@ -0,0 +1,21 @@
+module top #(
+ parameter WIDTH = 6
+) (
+ input [WIDTH-1:0] a_i,
+ input [WIDTH-1:0] b_i,
+ output [WIDTH-1:0] z_o
+);
+ genvar g;
+ generate
+ for (g = 0; g < WIDTH; g = g + 1) begin
+ if (g > 2) begin
+ wire tmp;
+ assign tmp = a_i[g] || b_i[g];
+ assign z_o[g] = tmp;
+ end
+ else begin
+ assign z_o[g] = a_i[g] && b_i[g];
+ end
+ end
+ endgenerate
+endmodule
diff --git a/tests/verilog/bug656.ys b/tests/verilog/bug656.ys
new file mode 100644
index 000000000..7f367341a
--- /dev/null
+++ b/tests/verilog/bug656.ys
@@ -0,0 +1,13 @@
+read_verilog bug656.v
+
+select -assert-count 1 top/a_i
+select -assert-count 1 top/b_i
+select -assert-count 1 top/z_o
+
+select -assert-none top/genblk1[0].genblk1.tmp
+select -assert-none top/genblk1[1].genblk1.tmp
+select -assert-none top/genblk1[2].genblk1.tmp
+
+select -assert-count 1 top/genblk1[3].genblk1.tmp
+select -assert-count 1 top/genblk1[4].genblk1.tmp
+select -assert-count 1 top/genblk1[5].genblk1.tmp
diff --git a/tests/verilog/genblk_case.v b/tests/verilog/genblk_case.v
new file mode 100644
index 000000000..081fb09d3
--- /dev/null
+++ b/tests/verilog/genblk_case.v
@@ -0,0 +1,26 @@
+module top;
+ parameter YES = 1;
+ generate
+ if (YES) wire y;
+ else wire n;
+
+ if (!YES) wire n;
+ else wire y;
+
+ case (YES)
+ 1: wire y;
+ 0: wire n;
+ endcase
+
+ case (!YES)
+ 0: wire y;
+ 1: wire n;
+ endcase
+
+ if (YES) wire y;
+ else wire n;
+
+ if (!YES) wire n;
+ else wire y;
+ endgenerate
+endmodule
diff --git a/tests/verilog/genblk_case.ys b/tests/verilog/genblk_case.ys
new file mode 100644
index 000000000..3c1bb51f9
--- /dev/null
+++ b/tests/verilog/genblk_case.ys
@@ -0,0 +1,15 @@
+read_verilog genblk_case.v
+
+select -assert-count 0 top/genblk1.n
+select -assert-count 0 top/genblk2.n
+select -assert-count 0 top/genblk3.n
+select -assert-count 0 top/genblk4.n
+select -assert-count 0 top/genblk5.n
+select -assert-count 0 top/genblk6.n
+
+select -assert-count 1 top/genblk1.y
+select -assert-count 1 top/genblk2.y
+select -assert-count 1 top/genblk3.y
+select -assert-count 1 top/genblk4.y
+select -assert-count 1 top/genblk5.y
+select -assert-count 1 top/genblk6.y
diff --git a/tests/verilog/genblk_port_decl.ys b/tests/verilog/genblk_port_decl.ys
new file mode 100644
index 000000000..589d3d2e1
--- /dev/null
+++ b/tests/verilog/genblk_port_decl.ys
@@ -0,0 +1,12 @@
+logger -expect error "Cannot declare module port `\\x' within a generate block\." 1
+read_verilog <<EOT
+module top(x);
+ generate
+ if (1) begin : blk
+ output wire x;
+ assign x = 1;
+ end
+ endgenerate
+ output wire x;
+endmodule
+EOT
diff --git a/tests/verilog/hidden_decl.ys b/tests/verilog/hidden_decl.ys
new file mode 100644
index 000000000..aed7847dc
--- /dev/null
+++ b/tests/verilog/hidden_decl.ys
@@ -0,0 +1,11 @@
+logger -expect error "Identifier `\\y' is implicitly declared and `default_nettype is set to none" 1
+read_verilog <<EOT
+`default_nettype none
+module top1;
+ wire x;
+ generate
+ if (1) wire y;
+ endgenerate
+ assign x = y;
+endmodule
+EOT
diff --git a/tests/verilog/unnamed_block.ys b/tests/verilog/unnamed_block.ys
new file mode 100644
index 000000000..0f209a089
--- /dev/null
+++ b/tests/verilog/unnamed_block.ys
@@ -0,0 +1,28 @@
+read_verilog <<EOT
+module top;
+ initial begin : blk
+ integer x;
+ end
+endmodule
+EOT
+
+delete
+
+read_verilog -sv <<EOT
+module top;
+ initial begin
+ integer x;
+ end
+endmodule
+EOT
+
+delete
+
+logger -expect error "Local declaration in unnamed block is only supported in SystemVerilog mode!" 1
+read_verilog <<EOT
+module top;
+ initial begin
+ integer x;
+ end
+endmodule
+EOT
diff --git a/tests/verilog/unnamed_genblk.sv b/tests/verilog/unnamed_genblk.sv
new file mode 100644
index 000000000..41828b1b0
--- /dev/null
+++ b/tests/verilog/unnamed_genblk.sv
@@ -0,0 +1,39 @@
+// This test is taken directly from Section 27.6 of IEEE 1800-2017
+
+module top;
+ parameter genblk2 = 0;
+ genvar i;
+
+ // The following generate block is implicitly named genblk1
+
+ if (genblk2) logic a; // top.genblk1.a
+ else logic b; // top.genblk1.b
+
+ // The following generate block is implicitly named genblk02
+ // as genblk2 is already a declared identifier
+
+ if (genblk2) logic a; // top.genblk02.a
+ else logic b; // top.genblk02.b
+
+ // The following generate block would have been named genblk3
+ // but is explicitly named g1
+
+ for (i = 0; i < 1; i = i + 1) begin : g1 // block name
+ // The following generate block is implicitly named genblk1
+ // as the first nested scope inside g1
+ if (1) logic a; // top.g1[0].genblk1.a
+ end
+
+ // The following generate block is implicitly named genblk4 since
+ // it belongs to the fourth generate construct in scope "top".
+ // The previous generate block would have been
+ // named genblk3 if it had not been explicitly named g1
+
+ for (i = 0; i < 1; i = i + 1)
+ // The following generate block is implicitly named genblk1
+ // as the first nested generate block in genblk4
+ if (1) logic a; // top.genblk4[0].genblk1.a
+
+ // The following generate block is implicitly named genblk5
+ if (1) logic a; // top.genblk5.a
+endmodule
diff --git a/tests/verilog/unnamed_genblk.ys b/tests/verilog/unnamed_genblk.ys
new file mode 100644
index 000000000..2b9aa9d69
--- /dev/null
+++ b/tests/verilog/unnamed_genblk.ys
@@ -0,0 +1,8 @@
+read_verilog -sv unnamed_genblk.sv
+select -assert-count 0 top/genblk1.a
+select -assert-count 1 top/genblk02.b
+select -assert-count 0 top/genblk1.a
+select -assert-count 1 top/genblk02.b
+select -assert-count 1 top/g1[0].genblk1.a
+select -assert-count 1 top/genblk4[0].genblk1.a
+select -assert-count 1 top/genblk5.a
diff --git a/tests/verilog/wire_and_var.sv b/tests/verilog/wire_and_var.sv
new file mode 100644
index 000000000..79c7c04c6
--- /dev/null
+++ b/tests/verilog/wire_and_var.sv
@@ -0,0 +1,33 @@
+`define TEST(kwd) \
+ kwd kwd``_1; \
+ kwd kwd``_2; \
+ initial kwd``_1 = 1; \
+ assign kwd``_2 = 1;
+
+`define TEST_VAR(kwd) \
+ var kwd var_``kwd``_1; \
+ var kwd var_``kwd``_2; \
+ initial var_``kwd``_1 = 1; \
+ assign var_``kwd``_2 = 1;
+
+`define TEST_WIRE(kwd) \
+ wire kwd wire_``kwd``_1; \
+ wire kwd wire_``kwd``_2; \
+ initial wire_``kwd``_1 = 1; \
+ assign wire_``kwd``_2 = 1;
+
+module top;
+
+`TEST(wire) // wire assigned in a block
+`TEST(reg) // reg assigned in a continuous assignment
+`TEST(logic)
+`TEST(integer)
+
+`TEST_VAR(reg) // reg assigned in a continuous assignment
+`TEST_VAR(logic)
+`TEST_VAR(integer)
+
+`TEST_WIRE(logic) // wire assigned in a block
+`TEST_WIRE(integer) // wire assigned in a block
+
+endmodule
diff --git a/tests/verilog/wire_and_var.ys b/tests/verilog/wire_and_var.ys
new file mode 100644
index 000000000..9359a9d55
--- /dev/null
+++ b/tests/verilog/wire_and_var.ys
@@ -0,0 +1,9 @@
+logger -expect warning "wire '\\wire_1' is assigned in a block" 1
+logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1
+
+logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1
+
+logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1
+logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1
+
+read_verilog -sv wire_and_var.sv
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 09:29:57 +0000