1 files changed, 0 insertions, 51 deletions
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
deleted file mode 100644
index 1923b9802..000000000
--- a/tests/xilinx/adffs.ys
+++ /dev/null
@@ -1,51 +0,0 @@
-read_verilog adffs.v
-design -save read
-
-hierarchy -top adff
-proc
-equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd adff # Constrain all select calls below inside the top module
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:FDCE
-
-select -assert-none t:BUFG t:FDCE %% t:* %D
-
-
-design -load read
-hierarchy -top adffn
-proc
-equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd adffn # Constrain all select calls below inside the top module
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:FDCE
-select -assert-count 1 t:LUT1
-
-select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
-
-
-design -load read
-hierarchy -top dffs
-proc
-equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dffs # Constrain all select calls below inside the top module
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:FDRE
-select -assert-count 1 t:LUT2
-
-select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
-
-
-design -load read
-hierarchy -top ndffnr
-proc
-equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd ndffnr # Constrain all select calls below inside the top module
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:FDRE_1
-select -assert-count 1 t:LUT2
-
-select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D