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Diffstat (limited to 'tests/xilinx/fsm.ys')
| -rw-r--r-- | tests/xilinx/fsm.ys | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys deleted file mode 100644 index a9e94c2c0..000000000 --- a/tests/xilinx/fsm.ys +++ /dev/null @@ -1,14 +0,0 @@ -read_verilog fsm.v -hierarchy -top fsm -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd fsm # Constrain all select calls below inside the top module - -select -assert-count 1 t:BUFG -select -assert-count 5 t:FDRE -select -assert-count 1 t:LUT3 -select -assert-count 2 t:LUT4 -select -assert-count 4 t:LUT6 -select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D |