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Diffstat (limited to 'tests/xilinx/mul.ys')
| -rw-r--r-- | tests/xilinx/mul.ys | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys deleted file mode 100644 index 66a06efdc..000000000 --- a/tests/xilinx/mul.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog mul.v -hierarchy -top top -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 1 t:DSP48E1 -select -assert-none t:DSP48E1 %% t:* %D |