diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/aiger/neg.ys | 36 | ||||
| -rwxr-xr-x | tests/aiger/run-test.sh | 5 | ||||
| -rw-r--r-- | tests/various/bug2014.ys | 12 | ||||
| -rw-r--r-- | tests/various/gen_if_null.v | 13 | ||||
| -rw-r--r-- | tests/various/gen_if_null.ys | 4 | ||||
| -rw-r--r-- | tests/various/primitives.ys | 16 | ||||
| -rw-r--r-- | tests/various/specify.ys | 6 |
7 files changed, 92 insertions, 0 deletions
diff --git a/tests/aiger/neg.ys b/tests/aiger/neg.ys new file mode 100644 index 000000000..4c1edd8a4 --- /dev/null +++ b/tests/aiger/neg.ys @@ -0,0 +1,36 @@ +read_verilog <<EOT +module top(input [31:-32] a, input [-65:-128] b, output [128:65] c); +assign c = a & b; +endmodule +EOT +select -assert-count 1 i:a +select -assert-count 1 i:b +select -assert-count 1 o:c +select -assert-count 3 x:* s:64 %i +design -save read + +!rm -rf neg.out +!mkdir neg.out +simplemap +write_aiger -map neg.out/neg.map neg.out/neg.aig + +design -reset +read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig +select -assert-count 1 i:a +select -assert-count 1 i:b +select -assert-count 1 o:c +select -assert-count 3 x:* s:64 %i + + +design -load read +!rm -rf neg.out +!mkdir neg.out +simplemap +write_xaiger -map neg.out/neg.map neg.out/neg.aig + +design -reset +read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig +select -assert-count 1 i:a +select -assert-count 1 i:b +select -assert-count 1 o:c +select -assert-count 3 x:* s:64 %i diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index 8e932b091..de7bc68cf 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -52,3 +52,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 16 miter " -l ${aig}.log done + +for y in *.ys; do + echo "Running $y." + ../../yosys $y -ql ${y%.*}.log +done diff --git a/tests/various/bug2014.ys b/tests/various/bug2014.ys new file mode 100644 index 000000000..10131fc43 --- /dev/null +++ b/tests/various/bug2014.ys @@ -0,0 +1,12 @@ +read_verilog <<EOT +module test ( + input signed [1:0] n, + output [3:0] dout +); + assign dout = n + 4'sd 4; +endmodule +EOT + +alumacc +select -assert-count 1 t:$alu +equiv_opt -assert opt -fine diff --git a/tests/various/gen_if_null.v b/tests/various/gen_if_null.v new file mode 100644 index 000000000..a12ac6288 --- /dev/null +++ b/tests/various/gen_if_null.v @@ -0,0 +1,13 @@ +module test(x, y, z); + localparam OFF = 0; + generate + if (OFF) ; + else input x; + if (!OFF) input y; + else ; + if (OFF) ; + else ; + if (OFF) ; + input z; + endgenerate +endmodule diff --git a/tests/various/gen_if_null.ys b/tests/various/gen_if_null.ys new file mode 100644 index 000000000..31dfc444b --- /dev/null +++ b/tests/various/gen_if_null.ys @@ -0,0 +1,4 @@ +read_verilog gen_if_null.v +select -assert-count 1 test/x +select -assert-count 1 test/y +select -assert-count 1 test/z diff --git a/tests/various/primitives.ys b/tests/various/primitives.ys new file mode 100644 index 000000000..9307ca50f --- /dev/null +++ b/tests/various/primitives.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module top(input a, b, output [5:0] y); +and (y[0], a, b); +nand (y[1], a, b); +or (y[2], a, b); +nor (y[3], a, b); +xor (y[4], a, b); +xnor (y[5], a, b); +endmodule +EOT +select -assert-count 1 t:$and a:src=<<EOT:2.4-2.17 %i +select -assert-count 1 t:$and a:src=<<EOT:3.5-3.18 %i +select -assert-count 1 t:$or a:src=<<EOT:4.3-4.16 %i +select -assert-count 1 t:$or a:src=<<EOT:5.4-5.17 %i +select -assert-count 1 t:$xor a:src=<<EOT:6.4-6.17 %i +select -assert-count 1 t:$xor a:src=<<EOT:7.5-7.18 %i diff --git a/tests/various/specify.ys b/tests/various/specify.ys index 9d55b8eb5..d7260d524 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -4,10 +4,16 @@ cd test select t:$specify2 -assert-count 0 select t:$specify3 -assert-count 1 select t:$specrule -assert-count 2 +select t:$specify3 a:src=specify.v:10.3-10.49 %i -assert-count 1 +select t:$specrule a:src=specify.v:11.3-11.36 %i -assert-count 1 +select t:$specrule a:src=specify.v:12.3-12.35 %i -assert-count 1 cd test2 select t:$specify2 -assert-count 2 select t:$specify3 -assert-count 0 select t:$specrule -assert-count 0 +select t:$specify2 a:src=specify.v:26.3-26.20 %i -assert-count 1 + # ^^ Note use of macro +select t:$specify2 a:src=specify.v:28.3-28.18 %i -assert-count 1 cd write_verilog specify.out design -stash gold |