aboutsummaryrefslogtreecommitdiffstats
path: root/tests
diff options
context:
space:
mode:
Diffstat (limited to 'tests')
-rw-r--r--tests/arch/ecp5/latches_abc9.ys13
-rw-r--r--tests/arch/ice40/mux.ys3
-rw-r--r--tests/arch/intel_alm/.gitignore2
-rw-r--r--tests/arch/xilinx/abc9_dff.ys57
-rw-r--r--tests/arch/xilinx/pmgen_xilinx_srl.ys2
-rw-r--r--tests/arch/xilinx/xilinx_srl.v2
-rw-r--r--tests/simple/constmuldivmod.v42
-rw-r--r--tests/svtypes/logic_rom.sv6
-rw-r--r--tests/svtypes/logic_rom.ys3
-rw-r--r--tests/svtypes/struct_array.sv22
-rw-r--r--tests/svtypes/struct_simple.sv48
-rw-r--r--tests/svtypes/typedef_struct.sv42
-rw-r--r--tests/svtypes/union_simple.sv72
-rw-r--r--tests/various/abc9.ys3
-rw-r--r--tests/various/attrib07_func_call.v2
-rw-r--r--tests/various/constmsk_testmap.v2
-rw-r--r--tests/various/printattr.ys14
-rw-r--r--tests/various/shregmap.v4
-rw-r--r--tests/verilog/bug2042-sv.ys2
19 files changed, 327 insertions, 14 deletions
diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys
new file mode 100644
index 000000000..4daf04050
--- /dev/null
+++ b/tests/arch/ecp5/latches_abc9.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top(input e, d, output q);
+reg l;
+always @*
+ if (e)
+ l = ~d;
+assign q = ~l;
+endmodule
+EOT
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ecp5 -abc9
+select -assert-count 2 t:LUT4
+select -assert-none t:LUT4 %% t:* %D
diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys
index 99822391d..2b661fd6b 100644
--- a/tests/arch/ice40/mux.ys
+++ b/tests/arch/ice40/mux.ys
@@ -35,6 +35,7 @@ proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 11 t:SB_LUT4
+select -assert-min 11 t:SB_LUT4
+select -assert-max 12 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/arch/intel_alm/.gitignore b/tests/arch/intel_alm/.gitignore
new file mode 100644
index 000000000..ba42e1ee6
--- /dev/null
+++ b/tests/arch/intel_alm/.gitignore
@@ -0,0 +1,2 @@
+/*.log
+/run-test.mk
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys
index fd343969b..210e87477 100644
--- a/tests/arch/xilinx/abc9_dff.ys
+++ b/tests/arch/xilinx/abc9_dff.ys
@@ -50,10 +50,10 @@ FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
endmodule
EOT
-logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$dff cell .*" 1
-logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$dff cell .*" 1
-logger -expect warning "Module 'FDSE' contains a \$dff cell .*" 1
-logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$dff cell .*" 1
+logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-count 8 t:FD*
@@ -82,4 +82,53 @@ select -assert-count 1 t:FDPE
select -assert-count 2 t:INV
select -assert-count 0 t:FD* t:INV %% t:* %D
+
+design -reset
+read_verilog <<EOT
+module top(input clk, input d, output q);
+reg r;
+always @(posedge clk) begin
+r <= d;
+end
+assign q = ~r;
+endmodule
+EOT
+proc
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-count 1 t:FDRE %co w:r %i
+
+
+design -reset
+read_verilog <<EOT
+module top(input clk, input a, b, output reg q1, output q2);
+reg r;
+always @(posedge clk) begin
+ q1 <= a | b;
+ r <= ~(~a & ~b);
+end
+assign q2 = r;
+endmodule
+EOT
+proc
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-count 1 t:FDRE %co %a w:r %i
+
+
+design -reset
+read_verilog <<EOT
+module top(input clk, input a, b, output o);
+reg r1, r2;
+always @(posedge clk) begin
+ r1 <= a | b;
+ r2 <= ~(~a & ~b);
+end
+assign o = r1 | r2;
+endmodule
+EOT
+proc
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+
+
logger -expect-no-warnings
diff --git a/tests/arch/xilinx/pmgen_xilinx_srl.ys b/tests/arch/xilinx/pmgen_xilinx_srl.ys
index ea2f20487..e76fb20ab 100644
--- a/tests/arch/xilinx/pmgen_xilinx_srl.ys
+++ b/tests/arch/xilinx/pmgen_xilinx_srl.ys
@@ -1,6 +1,6 @@
read_verilog -icells <<EOT
module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
- parameter DEPTH = 1;
+ parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = 0;
parameter CLKPOL = 1;
parameter ENPOL = 2;
diff --git a/tests/arch/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v
index bc2a15ab2..29920da41 100644
--- a/tests/arch/xilinx/xilinx_srl.v
+++ b/tests/arch/xilinx/xilinx_srl.v
@@ -29,7 +29,7 @@ endmodule
module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
-parameter DEPTH = 1;
+parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
diff --git a/tests/simple/constmuldivmod.v b/tests/simple/constmuldivmod.v
index d1d8be862..5dd8f9295 100644
--- a/tests/simple/constmuldivmod.v
+++ b/tests/simple/constmuldivmod.v
@@ -1,4 +1,4 @@
-module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y);
+module constmuldivmod(input [7:0] A, input [5:0] mode, output reg [7:0] Y);
always @* begin
case (mode)
0: Y = A / 8'd0;
@@ -21,6 +21,46 @@ module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y);
13: Y = A % 8'd8;
14: Y = A * 8'd8;
+ 15: Y = $signed(A) / $signed(8'd0);
+ 16: Y = $signed(A) % $signed(8'd0);
+ 17: Y = $signed(A) * $signed(8'd0);
+
+ 18: Y = $signed(A) / $signed(8'd1);
+ 19: Y = $signed(A) % $signed(8'd1);
+ 20: Y = $signed(A) * $signed(8'd1);
+
+ 21: Y = $signed(A) / $signed(8'd2);
+ 22: Y = $signed(A) % $signed(8'd2);
+ 23: Y = $signed(A) * $signed(8'd2);
+
+ 24: Y = $signed(A) / $signed(8'd4);
+ 25: Y = $signed(A) % $signed(8'd4);
+ 26: Y = $signed(A) * $signed(8'd4);
+
+ 27: Y = $signed(A) / $signed(8'd8);
+ 28: Y = $signed(A) % $signed(8'd8);
+ 29: Y = $signed(A) * $signed(8'd8);
+
+ 30: Y = $signed(A) / $signed(-8'd0);
+ 31: Y = $signed(A) % $signed(-8'd0);
+ 32: Y = $signed(A) * $signed(-8'd0);
+
+ 33: Y = $signed(A) / $signed(-8'd1);
+ 34: Y = $signed(A) % $signed(-8'd1);
+ 35: Y = $signed(A) * $signed(-8'd1);
+
+ 36: Y = $signed(A) / $signed(-8'd2);
+ 37: Y = $signed(A) % $signed(-8'd2);
+ 38: Y = $signed(A) * $signed(-8'd2);
+
+ 39: Y = $signed(A) / $signed(-8'd4);
+ 40: Y = $signed(A) % $signed(-8'd4);
+ 41: Y = $signed(A) * $signed(-8'd4);
+
+ 42: Y = $signed(A) / $signed(-8'd8);
+ 43: Y = $signed(A) % $signed(-8'd8);
+ 44: Y = $signed(A) * $signed(-8'd8);
+
default: Y = 8'd16 * A;
endcase
end
diff --git a/tests/svtypes/logic_rom.sv b/tests/svtypes/logic_rom.sv
new file mode 100644
index 000000000..45fe0a4ca
--- /dev/null
+++ b/tests/svtypes/logic_rom.sv
@@ -0,0 +1,6 @@
+module top(input [3:0] addr, output [7:0] data);
+ logic [7:0] mem[0:15];
+ assign data = mem[addr];
+ integer i;
+ initial for(i = 0; i < 16; i = i + 1) mem[i] = i;
+endmodule
diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys
new file mode 100644
index 000000000..7b079c136
--- /dev/null
+++ b/tests/svtypes/logic_rom.ys
@@ -0,0 +1,3 @@
+read_verilog -sv logic_rom.sv
+prep -top top
+select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i
diff --git a/tests/svtypes/struct_array.sv b/tests/svtypes/struct_array.sv
new file mode 100644
index 000000000..022ad56c6
--- /dev/null
+++ b/tests/svtypes/struct_array.sv
@@ -0,0 +1,22 @@
+// test for array indexing in structures
+
+module top;
+
+ struct packed {
+ bit [5:0] [7:0] a; // 6 element packed array of bytes
+ bit [15:0] b; // filler for non-zero offset
+ } s;
+
+ initial begin
+ s = '0;
+
+ s.a[2:1] = 16'h1234;
+ s.a[5] = 8'h42;
+
+ s.b = '1;
+ s.b[1:0] = '0;
+ end
+
+ always_comb assert(s==64'h4200_0012_3400_FFFC);
+
+endmodule
diff --git a/tests/svtypes/struct_simple.sv b/tests/svtypes/struct_simple.sv
new file mode 100644
index 000000000..c74289cc3
--- /dev/null
+++ b/tests/svtypes/struct_simple.sv
@@ -0,0 +1,48 @@
+module top;
+ localparam BITS=8;
+
+ struct packed {
+ logic a;
+ logic[BITS-1:0] b;
+ byte c;
+ logic x, y;
+ } s;
+
+ struct packed signed {
+ integer a;
+ logic[15:0] b;
+ logic[7:0] c;
+ bit [7:0] d;
+ } pack1;
+
+ struct packed {
+ byte a;
+ struct packed {
+ byte x, y;
+ } b;
+ } s2;
+
+ assign s.a = '1;
+ assign s.b = '1;
+ assign s.c = 8'hAA;
+ assign s.x = '1;
+ logic[7:0] t;
+ assign t = s.b;
+ assign pack1.a = 42;
+ assign pack1.b = 16'hAAAA;
+ assign pack1.c = '1;
+ assign pack1.d = 8'h55;
+ assign s2.b.x = 'h42;
+
+ always_comb assert(s.a == 1'b1);
+ always_comb assert(s.c == 8'hAA);
+ always_comb assert(s.x == 1'b1);
+ always_comb assert(t == 8'hFF);
+ always_comb assert(pack1.a == 42);
+ always_comb assert(pack1.b == 16'hAAAA);
+ always_comb assert(pack1.c == 8'hFF);
+ always_comb assert(pack1[15:8] == 8'hFF);
+ always_comb assert(pack1.d == 8'h55);
+ always_comb assert(s2.b.x == 'h42);
+
+endmodule
diff --git a/tests/svtypes/typedef_struct.sv b/tests/svtypes/typedef_struct.sv
new file mode 100644
index 000000000..7ae007952
--- /dev/null
+++ b/tests/svtypes/typedef_struct.sv
@@ -0,0 +1,42 @@
+package p;
+
+typedef struct packed {
+ byte a;
+ byte b;
+} p_t;
+
+endpackage
+
+
+module top;
+
+ typedef logic[7:0] t_t;
+
+ typedef struct packed {
+ bit a;
+ logic[7:0] b;
+ t_t t;
+ } s_t;
+
+ s_t s;
+ s_t s1;
+
+ p::p_t ps;
+
+ assign s.a = '1;
+ assign s.b = '1;
+ assign s.t = 8'h55;
+ assign s1 = s;
+ assign ps.a = 8'hAA;
+ assign ps.b = 8'h55;
+
+ always_comb begin
+ assert(s.a == 1'b1);
+ assert(s.b == 8'hFF);
+ assert(s.t == 8'h55);
+ assert(s1.t == 8'h55);
+ assert(ps.a == 8'hAA);
+ assert(ps.b == 8'h55);
+ end
+
+endmodule
diff --git a/tests/svtypes/union_simple.sv b/tests/svtypes/union_simple.sv
new file mode 100644
index 000000000..12e4b376f
--- /dev/null
+++ b/tests/svtypes/union_simple.sv
@@ -0,0 +1,72 @@
+module top;
+
+ typedef struct packed {
+ byte a,b,c,d;
+ } byte4_t;
+
+ typedef union packed {
+ int x;
+ byte4_t y;
+ } w_t;
+
+ w_t w;
+
+ assign w.x = 'h42;
+ always_comb begin
+ assert(w.y.d == 8'h42);
+ end
+
+ typedef logic[4:0] reg_addr_t;
+ typedef logic[6:0] opcode_t;
+
+ typedef struct packed {
+ bit [6:0] func7;
+ reg_addr_t rs2;
+ reg_addr_t rs1;
+ bit [2:0] func3;
+ reg_addr_t rd;
+ opcode_t opcode;
+ } R_t;
+
+ typedef struct packed {
+ bit[11:0] imm;
+ reg_addr_t rs1;
+ bit[2:0] func3;
+ reg_addr_t rd;
+ opcode_t opcode;
+ } I_t;
+
+ typedef struct packed {
+ bit[19:0] imm;
+ reg_addr_t rd;
+ opcode_t opcode;
+ } U_t;
+
+ typedef union packed {
+ R_t r;
+ I_t i;
+ U_t u;
+ } instruction_t;
+
+ instruction_t ir1;
+ assign ir1 = 32'h0AA01EB7; // lui t4,0xAA01
+ always_comb begin
+ assert(ir1.u.opcode == 'h37);
+ assert(ir1.r.opcode == 'h37);
+ assert(ir1.u.rd == 'd29);
+ assert(ir1.r.rd == 'd29);
+ assert(ir1.u.imm == 'hAA01);
+ end
+
+ union packed {
+ int word;
+ struct packed {
+ byte a, b, c, d;
+ } byte4;
+ } u;
+ assign u.word = 'h42;
+ always_comb begin
+ assert(u.byte4.d == 'h42);
+ end
+
+endmodule
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index ac714665f..a9880c722 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -97,4 +97,5 @@ select -assert-count 3 t:$_DFF_N_
select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
clean
select -assert-count 2 a:init
-select -assert-none w:w w:z %% a:init %D
+select -assert-count 1 w:w a:init %i
+select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i
diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v
index f55ef2316..8c9fb2926 100644
--- a/tests/various/attrib07_func_call.v
+++ b/tests/various/attrib07_func_call.v
@@ -11,7 +11,7 @@ module foo(clk, rst, inp_a, inp_b, out);
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
- output wire [7:0] out;
+ output reg [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
diff --git a/tests/various/constmsk_testmap.v b/tests/various/constmsk_testmap.v
index fab1b1bbc..b6809c7c0 100644
--- a/tests/various/constmsk_testmap.v
+++ b/tests/various/constmsk_testmap.v
@@ -1,7 +1,7 @@
(* techmap_celltype = "$reduce_or" *)
module my_opt_reduce_or(...);
parameter A_SIGNED = 0;
- parameter A_WIDTH = 1;
+ parameter A_WIDTH = 2;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
diff --git a/tests/various/printattr.ys b/tests/various/printattr.ys
new file mode 100644
index 000000000..afc6d8eb6
--- /dev/null
+++ b/tests/various/printattr.ys
@@ -0,0 +1,14 @@
+logger -expect log ".*cells_not_processed=[01]* .*" 1
+logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
+read_verilog <<EOT
+module mux2(a, b, s, y);
+ input a, b, s;
+ output y;
+
+ wire s_n = ~s;
+ wire t0 = s & a;
+ wire t1 = s_n & b;
+ assign y = t0 | t1;
+endmodule
+EOT
+printattrs
diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
index 604c2c976..dc828eda7 100644
--- a/tests/various/shregmap.v
+++ b/tests/various/shregmap.v
@@ -13,7 +13,7 @@ assign q = {shift2[3], shift1[3]};
endmodule
module $__SHREG_DFF_P_(input C, D, output Q);
-parameter DEPTH = 1;
+parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
always @(posedge C)
@@ -38,7 +38,7 @@ endmodule
module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
-parameter DEPTH = 1;
+parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
index e815d7fc5..91989f412 100644
--- a/tests/verilog/bug2042-sv.ys
+++ b/tests/verilog/bug2042-sv.ys
@@ -2,7 +2,7 @@ read_verilog -sv <<EOT
module Task_Test_Top
(
input a,
-output b
+output reg b
);
task SomeTaskName(a);
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-05 12:35:45 +0000