4 files changed, 100 insertions, 0 deletions
diff --git a/tests/various/fib.v b/tests/various/fib.v
new file mode 100644
index 000000000..986749626
--- /dev/null
+++ b/tests/various/fib.v
@@ -0,0 +1,65 @@
+module gate(
+    off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9
+);
+    input wire signed [31:0] off;
+
+    function automatic integer fib(
+        input integer k
+    );
+        if (k == 0)
+            fib = 0;
+        else if (k == 1)
+            fib = 1;
+        else
+            fib = fib(k - 1) + fib(k - 2);
+    endfunction
+
+    function automatic integer fib_wrap(
+        input integer k,
+        output integer o
+    );
+        o = off + fib(k);
+    endfunction
+
+    output integer fib0;
+    output integer fib1;
+    output integer fib2;
+    output integer fib3;
+    output integer fib4;
+    output integer fib5;
+    output integer fib6;
+    output integer fib7;
+    output integer fib8;
+    output integer fib9;
+
+    initial begin : blk
+        integer unused;
+        unused = fib_wrap(0, fib0);
+        unused = fib_wrap(1, fib1);
+        unused = fib_wrap(2, fib2);
+        unused = fib_wrap(3, fib3);
+        unused = fib_wrap(4, fib4);
+        unused = fib_wrap(5, fib5);
+        unused = fib_wrap(6, fib6);
+        unused = fib_wrap(7, fib7);
+        unused = fib_wrap(8, fib8);
+        unused = fib_wrap(9, fib9);
+    end
+endmodule
+
+module gold(
+    off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9
+);
+    input wire signed [31:0] off;
+
+    output integer fib0 = off + 0;
+    output integer fib1 = off + 1;
+    output integer fib2 = off + 1;
+    output integer fib3 = off + 2;
+    output integer fib4 = off + 3;
+    output integer fib5 = off + 5;
+    output integer fib6 = off + 8;
+    output integer fib7 = off + 13;
+    output integer fib8 = off + 21;
+    output integer fib9 = off + 34;
+endmodule
diff --git a/tests/various/fib.ys b/tests/various/fib.ys
new file mode 100644
index 000000000..946e0738a
--- /dev/null
+++ b/tests/various/fib.ys
@@ -0,0 +1,6 @@
+read_verilog fib.v
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/various/func_port_implied_dir.sv b/tests/various/func_port_implied_dir.sv
new file mode 100644
index 000000000..0424f1b46
--- /dev/null
+++ b/tests/various/func_port_implied_dir.sv
@@ -0,0 +1,23 @@
+module gate(w, x, y, z);
+	function automatic integer bar(
+		integer a
+	);
+		bar = 2 ** a;
+	endfunction
+	output integer w = bar(4);
+
+	function automatic integer foo(
+		input integer a, /* implicitly input */ integer b,
+		output integer c, /* implicitly output */ integer d
+	);
+		c = 42;
+		d = 51;
+		foo = a + b + 1;
+	endfunction
+	output integer x, y, z;
+	initial x = foo(1, 2, y, z);
+endmodule
+
+module gold(w, x, y, z);
+	output integer w = 16, x = 4, y = 42, z = 51;
+endmodule
diff --git a/tests/various/func_port_implied_dir.ys b/tests/various/func_port_implied_dir.ys
new file mode 100644
index 000000000..b5c22a05b
--- /dev/null
+++ b/tests/various/func_port_implied_dir.ys
@@ -0,0 +1,6 @@
+read_verilog -sv func_port_implied_dir.sv
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert