4 files changed, 95 insertions, 0 deletions
diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
new file mode 100644
index 000000000..bae63b5a4
--- /dev/null
+++ b/tests/xilinx/macc.v
@@ -0,0 +1,37 @@
+// Signed 40-bit streaming accumulator with 16-bit inputs
+// File: HDL_Coding_Techniques/multipliers/multipliers4.v
+//
+module macc # (parameter SIZEIN = /*16*/7, SIZEOUT = 40)
+ (input clk, ce, sload,
+ input signed [SIZEIN-1:0] a, b,
+ output signed [SIZEOUT-1:0] accum_out);
+ // Declare registers for intermediate values
+ reg signed [SIZEIN-1:0] a_reg, b_reg;
+ reg sload_reg;
+ reg signed [2*SIZEIN:0] mult_reg;
+ reg signed [SIZEOUT-1:0] adder_out, old_result;
+ always @(adder_out or sload_reg) begin
+ //if (sload_reg)
+ //old_result <= 0;
+ //else
+ // 'sload' is now active (=low) and opens the accumulation loop.
+ // The accumulator takes the next multiplier output in
+ // the same cycle.
+ old_result <= adder_out;
+ a_reg <= a;
+ b_reg <= b;
+ end
+
+ always @(posedge clk)
+ //if (ce)
+ begin
+ mult_reg <= a_reg * b_reg;
+ sload_reg <= sload;
+ // Store accumulation result into a register
+ adder_out <= old_result + mult_reg;
+ end
+
+ // Output accumulation result
+ assign accum_out = adder_out;
+
+endmodule // macc
diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys
new file mode 100644
index 000000000..62b69f4d2
--- /dev/null
+++ b/tests/xilinx/macc.ys
@@ -0,0 +1,17 @@
+read_verilog macc.v
+proc
+hierarchy -top macc
+equiv_opt -run :restore -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+
+#equiv_miter -trigger miter equiv
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+#equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+#miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -set-init-zero -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd macc # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:DSP48E1
+select -assert-none t:BUFG t:DSP48E1 %% t:* %D
diff --git a/tests/xilinx/mul_unsigned.v b/tests/xilinx/mul_unsigned.v
new file mode 100644
index 000000000..e3713a642
--- /dev/null
+++ b/tests/xilinx/mul_unsigned.v
@@ -0,0 +1,30 @@
+/*
+Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89].
+*/
+
+// Unsigned 16x24-bit Multiplier
+// 1 latency stage on operands
+// 3 latency stage after the multiplication
+// File: multipliers2.v
+//
+module mul_unsigned (clk, A, B, RES);
+parameter WIDTHA = /*16*/ 6;
+parameter WIDTHB = /*24*/ 9;
+input clk;
+input [WIDTHA-1:0] A;
+input [WIDTHB-1:0] B;
+output [WIDTHA+WIDTHB-1:0] RES;
+reg [WIDTHA-1:0] rA;
+reg [WIDTHB-1:0] rB;
+reg [WIDTHA+WIDTHB-1:0] M [3:0];
+integer i;
+always @(posedge clk)
+ begin
+ rA <= A;
+ rB <= B;
+ M[0] <= rA * rB;
+ for (i = 0; i < 3; i = i+1)
+ M[i+1] <= M[i];
+ end
+assign RES = M[3];
+endmodule
diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys
new file mode 100644
index 000000000..30c034afe
--- /dev/null
+++ b/tests/xilinx/mul_unsigned.ys
@@ -0,0 +1,11 @@
+read_verilog mul_unsigned.v
+proc
+hierarchy -top mul_unsigned
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mul_unsigned # Constrain all select calls below inside the top module
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:DSP48E1
+select -assert-count 30 t:FDRE
+select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D