22 files changed, 376 insertions, 22 deletions
diff --git a/tests/arch/gowin/.gitignore b/tests/arch/gowin/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/arch/gowin/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/arch/gowin/add_sub.ys b/tests/arch/gowin/add_sub.ys
new file mode 100644
index 000000000..9b53dc0a9
--- /dev/null
+++ b/tests/arch/gowin/add_sub.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:ALU
+select -assert-count 8 t:OBUF
+select -assert-count 8 t:IBUF
+select -assert-count 1 t:GND
+select -assert-count 1 t:VCC
+select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D
+
diff --git a/tests/arch/gowin/adffs.ys b/tests/arch/gowin/adffs.ys
new file mode 100644
index 000000000..fc7ee01f2
--- /dev/null
+++ b/tests/arch/gowin/adffs.ys
@@ -0,0 +1,55 @@
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+stat
+select -assert-count 1 t:DFFC
+select -assert-count 3 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D
+
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFC
+select -assert-count 1 t:LUT1
+select -assert-count 3 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D
+
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFS
+select -assert-count 4 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D
+
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFNR
+select -assert-count 1 t:LUT1
+select -assert-count 4 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D
diff --git a/tests/arch/gowin/counter.ys b/tests/arch/gowin/counter.ys
new file mode 100644
index 000000000..920479d44
--- /dev/null
+++ b/tests/arch/gowin/counter.ys
@@ -0,0 +1,15 @@
+read_verilog ../common/counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8 t:DFFC
+select -assert-count 8 t:ALU
+select -assert-count 1 t:GND
+select -assert-count 1 t:VCC
+select -assert-count 2 t:IBUF
+select -assert-count 8 t:OBUF
+select -assert-none t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D
diff --git a/tests/arch/gowin/dffs.ys b/tests/arch/gowin/dffs.ys
new file mode 100644
index 000000000..9c012213f
--- /dev/null
+++ b/tests/arch/gowin/dffs.ys
@@ -0,0 +1,25 @@
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFF
+select -assert-count 2 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFE
+select -assert-count 3 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFE t:IBUF t:OBUF %% t:* %D
diff --git a/tests/arch/gowin/fsm.ys b/tests/arch/gowin/fsm.ys
new file mode 100644
index 000000000..ce4504522
--- /dev/null
+++ b/tests/arch/gowin/fsm.ys
@@ -0,0 +1,11 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+#design -load postopt
+#shell
diff --git a/tests/arch/gowin/logic.ys b/tests/arch/gowin/logic.ys
new file mode 100644
index 000000000..d2b9e4540
--- /dev/null
+++ b/tests/arch/gowin/logic.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:LUT1
+select -assert-count 6 t:LUT2
+select -assert-count 2 t:LUT4
+select -assert-count 8 t:IBUF
+select -assert-count 10 t:OBUF
+select -assert-none t:LUT1 t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D
diff --git a/tests/arch/gowin/memory.ys b/tests/arch/gowin/memory.ys
new file mode 100644
index 000000000..8f88cdd7c
--- /dev/null
+++ b/tests/arch/gowin/memory.ys
@@ -0,0 +1,18 @@
+read_verilog ../common/memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#ERROR: Called with -verify and proof did fail!
+#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 8 t:RAM16S4
+# other logic present that is not simple
+#select -assert-none t:RAM16S4 %% t:* %D
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
new file mode 100644
index 000000000..afad29a89
--- /dev/null
+++ b/tests/arch/gowin/mux.ys
@@ -0,0 +1,49 @@
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 3 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 4 t:LUT4
+select -assert-count 2 t:MUX2_LUT5
+select -assert-count 1 t:MUX2_LUT6
+select -assert-count 6 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 11 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 20 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D
diff --git a/tests/arch/gowin/run-test.sh b/tests/arch/gowin/run-test.sh
new file mode 100755
index 000000000..bf19b887d
--- /dev/null
+++ b/tests/arch/gowin/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/arch/gowin/shifter.ys b/tests/arch/gowin/shifter.ys
new file mode 100644
index 000000000..b43b1e869
--- /dev/null
+++ b/tests/arch/gowin/shifter.ys
@@ -0,0 +1,12 @@
+read_verilog ../common/shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8  t:DFF
+select -assert-count 2  t:IBUF
+select -assert-count 8  t:OBUF
+select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D
diff --git a/tests/arch/gowin/tribuf.ys b/tests/arch/gowin/tribuf.ys
new file mode 100644
index 000000000..5855b9d97
--- /dev/null
+++ b/tests/arch/gowin/tribuf.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/gowin/cells_sim.v -map +/simcells.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+#Internal cell type used. Need support it.
+select -assert-count 1 t:TBUF
+select -assert-count 2 t:IBUF
+select -assert-none t:TBUF t:IBUF %% t:* %D
diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys
index 12c34415e..e73bfe0b9 100644
--- a/tests/arch/xilinx/adffs.ys
+++ b/tests/arch/xilinx/adffs.ys
@@ -20,9 +20,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDCE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 
-select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
+select -assert-none t:BUFG t:FDCE t:INV %% t:* %D
 
 
 design -load read
diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys
index 57b645d19..604acdbfc 100644
--- a/tests/arch/xilinx/counter.ys
+++ b/tests/arch/xilinx/counter.ys
@@ -8,7 +8,7 @@ cd top # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:BUFG
 select -assert-count 8 t:FDCE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 select -assert-count 7 t:MUXCY
 select -assert-count 8 t:XORCY
-select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D
+select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D
diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys
index fe7887e8d..c87a8e38b 100644
--- a/tests/arch/xilinx/latches.ys
+++ b/tests/arch/xilinx/latches.ys
@@ -18,9 +18,9 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalen
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 
-select -assert-none t:LDCE t:LUT1 %% t:* %D
+select -assert-none t:LDCE t:INV %% t:* %D
 
 
 design -load read
diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys
index c0f6da302..d5b5c1a37 100644
--- a/tests/arch/xilinx/logic.ys
+++ b/tests/arch/xilinx/logic.ys
@@ -5,7 +5,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 select -assert-count 6 t:LUT2
 select -assert-count 2 t:LUT4
-select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D
+select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D
diff --git a/tests/opt/bug1525.ys b/tests/opt/bug1525.ys
new file mode 100644
index 000000000..972bc0ac7
--- /dev/null
+++ b/tests/opt/bug1525.ys
@@ -0,0 +1,13 @@
+read_verilog << EOF
+module top(...);
+input A1, A2, B, S;
+output O;
+
+assign O = S ? (A1 & B) : (A2 & B);
+
+endmodule
+EOF
+
+simplemap
+opt_share
+dump
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 64b625efe..4d5879e6f 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -218,12 +218,6 @@ module MUXF8(input I0, I1, S, output O);
 endmodule
 
 // Citation: https://github.com/alexforencich/verilog-ethernet
-// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q
-// returns before b4321a31
-//   Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no
-//   driver.
-//   Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no
-//   driver.
 module abc9_test022
 (
     input  wire        clk,
@@ -237,9 +231,6 @@ module abc9_test022
 endmodule
 
 // Citation: https://github.com/riscv/riscv-bitmanip
-// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q
-// returns before 14233843
-//   Warning: Wire abc9_test023.\dout [1] is used but has no driver.
 module abc9_test023 #(
 	parameter integer N = 2,
 	parameter integer M = 2
diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys
index f1277864e..b81a35e74 100644
--- a/tests/techmap/clkbufmap.ys
+++ b/tests/techmap/clkbufmap.ys
@@ -4,6 +4,7 @@ module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule
 module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule
 module latch (input e, d, output q); endmodule
 module clkgen (output o); endmodule
+module inv ((* clkbuf_inv = "i" *) output o, input i); endmodule
 
 module top(input clk1, clk2, clk3, d, e, output [4:0] q);
 wire clk4, clk5, clk6;
@@ -17,12 +18,18 @@ dff s6 (.clk(clk6), .d(d), .q(q[4]));
 endmodule
 
 module sub(output sclk4, output sclk5, output sclk6, input sd, output sq);
+wire sclk7, sclk8, sclk9;
+wire siq;
 wire tmp;
 clkgen s7(.o(sclk4));
 clkgen s8(.o(sclk5));
 clkgen s9(.o(tmp));
-clkbuf s10(.i(tmp), .o(sclk6));
-dff s11(.clk(sclk4), .d(sd), .q(sq));
+clkbuf s10(.i(tmp), .o(sclk7));
+dff s11(.clk(sclk4), .d(sd), .q(siq));
+inv s15(.i(sclk7), .o(sclk6));
+clkgen s12(.o(sclk8));
+inv s13(.o(sclk9), .i(sclk8));
+dff s14(.clk(sclk9), .d(siq), .q(sq));
 endmodule
 EOT
 
@@ -34,7 +41,7 @@ design -save ref
 design -load ref
 clkbufmap -buf clkbuf o:i
 select -assert-count 3 top/t:clkbuf
-select -assert-count 2 sub/t:clkbuf
+select -assert-count 3 sub/t:clkbuf
 select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
 select -assert-count 1 @clk1                        # Check there is one such fanout
 select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
@@ -51,6 +58,10 @@ select -set sclk4 w:sclk4 %a %ci t:clkbuf %i
 select -assert-count 1 @sclk4
 select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i
 select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i
+select -set sclk8 w:sclk8 %a %ci t:clkbuf %i
+select -assert-count 1 @sclk8
+select -assert-count 1 @sclk8 %x:+[o] %co c:s13 %i
+select -assert-count 1 @sclk8 %x:+[i] %ci c:s12 %i
 
 # ----------------------
 
@@ -72,7 +83,7 @@ setattr -set clkbuf_inhibit 1 w:clk1
 setattr -set buffer_type "bufg" w:clk2
 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
 select -assert-count 3 top/t:clkbuf
-select -assert-count 2 sub/t:clkbuf
+select -assert-count 3 sub/t:clkbuf
 select -set clk1 w:clk1 %a %co t:clkbuf %i          # Find 'clk1' fanouts that are 'clkbuf'
 select -assert-count 1 @clk1                        # Check there is one such fanout
 select -assert-count 1 @clk1 %x:+[o] %co c:s* %i    # Check that the 'o' of that clkbuf drives one fanout
@@ -93,4 +104,4 @@ clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
 select -assert-count 0 w:clk1 %a %co t:clkbuf %i
 select -assert-count 0 w:clk2 %a %co t:clkbuf %i
 select -assert-count 0 top/t:clkbuf
-select -assert-count 1 sub/t:clkbuf
+select -assert-count 2 sub/t:clkbuf
diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys
new file mode 100644
index 000000000..15cab5121
--- /dev/null
+++ b/tests/various/bug1462.ys
@@ -0,0 +1,11 @@
+read_verilog << EOF
+module top(...);
+input wire [31:0] A;
+output wire [31:0] P;
+
+assign P = A * 32'h12300000;
+
+endmodule
+EOF
+
+synth_xilinx
diff --git a/tests/various/bug1480.ys b/tests/various/bug1480.ys
new file mode 100644
index 000000000..84faea08a
--- /dev/null
+++ b/tests/various/bug1480.ys
@@ -0,0 +1,18 @@
+read_verilog << EOF
+module top(...);
+
+input signed [17:0] A;
+input signed [17:0] B;
+output X;
+output Y;
+
+wire [35:0] P;
+assign P = A * B;
+
+assign X = P[0];
+assign Y = P[35];
+
+endmodule
+EOF
+
+synth_xilinx
diff --git a/tests/various/svalways.sh b/tests/various/svalways.sh
new file mode 100755
index 000000000..2cc09f801
--- /dev/null
+++ b/tests/various/svalways.sh
@@ -0,0 +1,63 @@
+#!/bin/bash
+
+trap 'echo "ERROR in svalways.sh" >&2; exit 1' ERR
+
+# Good case
+../../yosys -f "verilog -sv" -qp proc - <<EOT
+module top(input clk, en, d, output reg p, q, r);
+
+always_ff @(posedge clk)
+	p <= d;
+
+always_comb
+	q = ~d;
+
+always_latch
+	if (en) r = d;
+
+endmodule
+EOT
+
+# Incorrect always_comb syntax
+((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
+module top(input d, output reg q);
+
+always_comb @(d)
+	q = ~d;
+
+endmodule
+EOT
+) 2>&1 | grep -F "<stdin>:3: ERROR: syntax error, unexpected '@'" > /dev/null
+
+# Incorrect use of always_comb
+((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
+module top(input en, d, output reg q);
+
+always_comb
+	if (en) q = d;
+
+endmodule
+EOT
+) 2>&1 | grep -F "ERROR: Latch inferred for signal \`\\top.\\q' from always_comb process" > /dev/null
+
+# Incorrect use of always_latch
+((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
+module top(input en, d, output reg q);
+
+always_latch
+	q = !d;
+
+endmodule
+EOT
+) 2>&1 | grep -F "ERROR: No latch inferred for signal \`\\top.\\q' from always_latch process" > /dev/null
+
+# Incorrect use of always_ff
+((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
+module top(input en, d, output reg q);
+
+always_ff @(*)
+	q = !d;
+
+endmodule
+EOT
+) 2>&1 | grep -F "ERROR: Found non edge/level sensitive event in always_ff process" > /dev/null