24 files changed, 305 insertions, 136 deletions
diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys
new file mode 100644
index 000000000..4daf04050
--- /dev/null
+++ b/tests/arch/ecp5/latches_abc9.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top(input e, d, output q);
+reg l;
+always @*
+    if (e)
+        l = ~d;
+assign q = ~l;
+endmodule
+EOT
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ecp5 -abc9
+select -assert-count 2 t:LUT4
+select -assert-none t:LUT4 %% t:* %D
diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys
index 99822391d..2b661fd6b 100644
--- a/tests/arch/ice40/mux.ys
+++ b/tests/arch/ice40/mux.ys
@@ -35,6 +35,7 @@ proc
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 11 t:SB_LUT4
+select -assert-min 11 t:SB_LUT4
+select -assert-max 12 t:SB_LUT4
 
 select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys
index b457cefce..fd343969b 100644
--- a/tests/arch/xilinx/abc9_dff.ys
+++ b/tests/arch/xilinx/abc9_dff.ys
@@ -1,32 +1,85 @@
+logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*"
+
+read_verilog <<EOT
+module top(input C, D, output [7:0] Q);
+FDRE   /*#(.INIT(0))*/ fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
+FDSE   #(.INIT(0)) fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
+FDCE   #(.INIT(0)) fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
+FDPE   #(.INIT(0)) fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
+FDRE_1 #(.INIT(0)) fd5(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[4]));
+FDSE_1 #(.INIT(0)) fd6(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[5]));
+FDCE_1 #(.INIT(0)) fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6]));
+FDPE_1 #(.INIT(0)) fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7]));
+endmodule
+EOT
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-count 6 t:FD*
+select -assert-count 6 c:fd2 c:fd3 c:fd4 c:fd6 c:fd7 c:fd8
+
+
+design -reset
 read_verilog <<EOT
 module top(input C, D, output [7:0] Q);
-FDRE   fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
-FDSE   fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
-FDCE   fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
-FDPE   fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
-FDRE_1 fd5(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[4]));
-FDSE_1 fd6(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[5]));
-FDCE_1 fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6]));
-FDPE_1 fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7]));
+FDRE   #(.INIT(0)) fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
+FDSE   #(.INIT(0)) fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
+FDCE   #(.INIT(0)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
+FDPE   #(.INIT(0)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
+FDRE_1 /*#(.INIT(0))*/ fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
+FDSE_1 #(.INIT(0)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
+FDCE_1 #(.INIT(0)) fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
+FDPE_1 #(.INIT(0)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
 endmodule
 EOT
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
-select -assert-none t:FD*
+select -assert-count 4 t:FD*
+select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8
+
 
 design -reset
 read_verilog <<EOT
 module top(input C, D, output [7:0] Q);
-FDRE   fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
-FDSE   fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
-FDCE   fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
-FDPE   fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
-FDRE_1 fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
-FDSE_1 fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
-FDCE_1 fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
-FDPE_1 fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
+FDRE   #(.INIT(1)) fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
+FDSE   /*#(.INIT(1))*/ fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
+FDCE   #(.INIT(1)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
+FDPE   #(.INIT(1)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
+FDRE_1 #(.INIT(1)) fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
+FDSE_1 #(.INIT(1)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
+FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
+FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
+endmodule
+EOT
+logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$dff cell .*" 1
+logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$dff cell .*" 1
+logger -expect warning "Module 'FDSE' contains a \$dff cell .*" 1
+logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$dff cell .*" 1
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-count 8 t:FD*
+
+
+design -reset
+read_verilog <<EOT
+module top(input clk, clr, pre, output reg q0 = 1'b0, output reg q1 = 1'b1);
+always @(posedge clk or posedge clr)
+    if (clr)
+        q0 <= 1'b0;
+    else
+        q0 <= ~q0;
+always @(posedge clk or posedge pre)
+    if (pre)
+        q1 <= 1'b1;
+    else
+        q1 <= ~q1;
 endmodule
 EOT
+proc
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
-select -assert-none t:FD*
+select -assert-count 1 t:FDCE
+select -assert-count 1 t:FDPE
+select -assert-count 2 t:INV
+select -assert-count 0 t:FD* t:INV %% t:* %D
+
+logger -expect-no-warnings
diff --git a/tests/arch/xilinx/abc9_map.ys b/tests/arch/xilinx/abc9_map.ys
deleted file mode 100644
index 4a7b9384a..000000000
--- a/tests/arch/xilinx/abc9_map.ys
+++ /dev/null
@@ -1,91 +0,0 @@
-read_verilog <<EOT
-module top(input C, CE, D, R, output [1:0] Q);
-FDRE   #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .R(R), .Q(Q[0]));
-FDRE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .R(R), .Q(Q[1]));
-endmodule
-EOT
-design -save gold
-
-techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
-techmap -map +/xilinx/abc9_unmap.v
-select -assert-count 1 t:FDSE
-select -assert-count 1 t:FDSE_1
-techmap -autoproc -map +/xilinx/cells_sim.v
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-techmap -autoproc -map +/xilinx/cells_sim.v
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 2 -verify -prove-asserts -show-ports miter
-
-design -reset
-read_verilog <<EOT
-module top(input C, CE, D, S, output [1:0] Q);
-FDSE   #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .S(S), .Q(Q[0]));
-FDSE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .S(S), .Q(Q[1]));
-endmodule
-EOT
-design -save gold
-
-techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
-techmap -map +/xilinx/abc9_unmap.v
-select -assert-count 1 t:FDRE
-select -assert-count 1 t:FDRE_1
-techmap -autoproc -map +/xilinx/cells_sim.v
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-techmap -autoproc -map +/xilinx/cells_sim.v
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 2 -set-init-zero -verify -prove-asserts -show-ports miter
-
-design -reset
-read_verilog <<EOT
-module top(input C, CE, D, PRE, output [1:0] Q);
-FDPE   #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q[0]));
-FDPE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q[1]));
-endmodule
-EOT
-design -save gold
-
-techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
-techmap -map +/xilinx/abc9_unmap.v
-select -assert-count 1 t:FDCE
-select -assert-count 1 t:FDCE_1
-techmap -autoproc -map +/xilinx/cells_sim.v
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-techmap -autoproc -map +/xilinx/cells_sim.v
-clk2fflogic
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 2 -set-init-zero -verify -prove-asserts -show-ports miter
-
-design -reset
-read_verilog <<EOT
-module top(input C, CE, D, CLR, output [1:0] Q);
-FDCE   #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q[0]));
-FDCE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q[1]));
-endmodule
-EOT
-design -save gold
-
-techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
-techmap -map +/xilinx/abc9_unmap.v
-select -assert-count 1 t:FDPE
-techmap -autoproc -map +/xilinx/cells_sim.v
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-techmap -autoproc -map +/xilinx/cells_sim.v
-clk2fflogic
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 2 -set-init-zero -verify -prove-asserts -show-ports miter
diff --git a/tests/arch/xilinx/macc.v b/tests/arch/xilinx/macc.v
index e36b2bab1..1645537fd 100644
--- a/tests/arch/xilinx/macc.v
+++ b/tests/arch/xilinx/macc.v
@@ -10,10 +10,10 @@ module macc # (parameter SIZEIN = 16, SIZEOUT = 40) (
 	output signed [SIZEOUT-1:0] accum_out
 );
 // Declare registers for intermediate values
-reg signed [SIZEIN-1:0] a_reg, b_reg;
-reg sload_reg;
-reg signed [2*SIZEIN-1:0] mult_reg;
-reg signed [SIZEOUT-1:0] adder_out, old_result;
+reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0;
+reg sload_reg = 0;
+reg signed [2*SIZEIN-1:0] mult_reg = 0;
+reg signed [SIZEOUT-1:0] adder_out = 0, old_result;
 always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
 	if (sload_reg)
 		old_result <= 0;
@@ -50,10 +50,10 @@ module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
 	output overflow
 );
 // Declare registers for intermediate values
-reg signed [SIZEIN-1:0] a_reg, b_reg, a_reg2, b_reg2;
+reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0, a_reg2 = 0, b_reg2 = 0;
 reg signed [2*SIZEIN-1:0] mult_reg = 0;
 reg signed [SIZEOUT:0] adder_out = 0;
-reg overflow_reg;
+reg overflow_reg = 0;
 always @(posedge clk) begin
 	//if (ce)
 	begin
diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys
index bf2b36320..61a570f48 100644
--- a/tests/arch/xilinx/macc.ys
+++ b/tests/arch/xilinx/macc.ys
@@ -6,7 +6,7 @@ proc
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
+sat -verify -prove-asserts -seq 3 -show-inputs -show-outputs miter
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd macc # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -20,7 +20,7 @@ proc
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
+sat -verify -prove-asserts -seq 4 -show-inputs -show-outputs miter
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd macc2 # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys
index 99817738d..1b2788448 100644
--- a/tests/arch/xilinx/mux.ys
+++ b/tests/arch/xilinx/mux.ys
@@ -40,8 +40,10 @@ proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-min 5 t:LUT6
+select -assert-max 2 t:LUT4
+select -assert-min 4 t:LUT6
 select -assert-max 7 t:LUT6
 select -assert-max 2 t:MUXF7
+dump
 
-select -assert-none t:LUT6 t:MUXF7 %% t:* %D
+select -assert-none t:LUT6 t:LUT4 t:MUXF7 %% t:* %D
diff --git a/tests/arch/xilinx/pmgen_xilinx_srl.ys b/tests/arch/xilinx/pmgen_xilinx_srl.ys
index ea2f20487..e76fb20ab 100644
--- a/tests/arch/xilinx/pmgen_xilinx_srl.ys
+++ b/tests/arch/xilinx/pmgen_xilinx_srl.ys
@@ -1,6 +1,6 @@
 read_verilog -icells <<EOT
 module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
-  parameter DEPTH = 1;
+  parameter DEPTH = 2;
   parameter [DEPTH-1:0] INIT = 0;
   parameter CLKPOL = 1;
   parameter ENPOL = 2;
diff --git a/tests/arch/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v
index bc2a15ab2..29920da41 100644
--- a/tests/arch/xilinx/xilinx_srl.v
+++ b/tests/arch/xilinx/xilinx_srl.v
@@ -29,7 +29,7 @@ endmodule
 module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
 parameter CLKPOL = 1;
 parameter ENPOL = 1;
-parameter DEPTH = 1;
+parameter DEPTH = 2;
 parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
 reg [DEPTH-1:0] r = INIT;
 wire clk = C ^ CLKPOL;
diff --git a/tests/simple/constmuldivmod.v b/tests/simple/constmuldivmod.v
index d1d8be862..5dd8f9295 100644
--- a/tests/simple/constmuldivmod.v
+++ b/tests/simple/constmuldivmod.v
@@ -1,4 +1,4 @@
-module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y);
+module constmuldivmod(input [7:0] A, input [5:0] mode, output reg [7:0] Y);
 	always @* begin
 		case (mode)
 			0: Y = A / 8'd0;
@@ -21,6 +21,46 @@ module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y);
 			13: Y = A % 8'd8;
 			14: Y = A * 8'd8;
 
+			15: Y = $signed(A) / $signed(8'd0);
+			16: Y = $signed(A) % $signed(8'd0);
+			17: Y = $signed(A) * $signed(8'd0);
+
+			18: Y = $signed(A) / $signed(8'd1);
+			19: Y = $signed(A) % $signed(8'd1);
+			20: Y = $signed(A) * $signed(8'd1);
+
+			21: Y = $signed(A) / $signed(8'd2);
+			22: Y = $signed(A) % $signed(8'd2);
+			23: Y = $signed(A) * $signed(8'd2);
+
+			24: Y = $signed(A) / $signed(8'd4);
+			25: Y = $signed(A) % $signed(8'd4);
+			26: Y = $signed(A) * $signed(8'd4);
+
+			27: Y = $signed(A) / $signed(8'd8);
+			28: Y = $signed(A) % $signed(8'd8);
+			29: Y = $signed(A) * $signed(8'd8);
+
+			30: Y = $signed(A) / $signed(-8'd0);
+			31: Y = $signed(A) % $signed(-8'd0);
+			32: Y = $signed(A) * $signed(-8'd0);
+
+			33: Y = $signed(A) / $signed(-8'd1);
+			34: Y = $signed(A) % $signed(-8'd1);
+			35: Y = $signed(A) * $signed(-8'd1);
+
+			36: Y = $signed(A) / $signed(-8'd2);
+			37: Y = $signed(A) % $signed(-8'd2);
+			38: Y = $signed(A) * $signed(-8'd2);
+
+			39: Y = $signed(A) / $signed(-8'd4);
+			40: Y = $signed(A) % $signed(-8'd4);
+			41: Y = $signed(A) * $signed(-8'd4);
+
+			42: Y = $signed(A) / $signed(-8'd8);
+			43: Y = $signed(A) % $signed(-8'd8);
+			44: Y = $signed(A) * $signed(-8'd8);
+
 			default: Y = 8'd16 * A;
 		endcase
 	end
diff --git a/tests/simple_abc9/abc9.box b/tests/simple_abc9/abc9.box
new file mode 100644
index 000000000..b3c88437c
--- /dev/null
+++ b/tests/simple_abc9/abc9.box
@@ -0,0 +1,3 @@
+MUXF8 1 0 3 1
+#I0 I1 S
+0 0 0 # O
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 688b47586..5e969c614 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode
   input rst;
 endmodule
 
-(* abc9_box, blackbox *)
+(* abc9_box_id=1, blackbox *)
 module MUXF8(input I0, I1, S, output O);
 specify
     (I0 => O) = 0;
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 424d8f417..650e42fca 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -25,7 +25,7 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p
     synth -run coarse; \
     opt -full; \
     techmap; \
-    abc9 -lut 4; \
+    abc9 -lut 4 -box ../abc9.box; \
     clean; \
     check -assert; \
     select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \
diff --git a/tests/svtypes/logic_rom.sv b/tests/svtypes/logic_rom.sv
new file mode 100644
index 000000000..45fe0a4ca
--- /dev/null
+++ b/tests/svtypes/logic_rom.sv
@@ -0,0 +1,6 @@
+module top(input [3:0] addr, output [7:0] data);
+    logic [7:0] mem[0:15];
+    assign data = mem[addr];
+    integer i;
+    initial for(i = 0; i < 16; i = i + 1) mem[i] = i;
+endmodule
diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys
new file mode 100644
index 000000000..7b079c136
--- /dev/null
+++ b/tests/svtypes/logic_rom.ys
@@ -0,0 +1,3 @@
+read_verilog -sv logic_rom.sv
+prep -top top
+select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 6e2415ad7..ac714665f 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -45,14 +45,16 @@ sat -seq 10 -verify -prove-asserts -show-ports miter
 design -reset
 read_verilog -icells <<EOT
 module abc9_test036(input clk, d, output q);
-(* keep *) reg w;
-$__ABC9_FF_ ff(.D(d), .Q(w));
-wire \ff.clock = clk;
-wire \ff.init = 1'b0;
+(* keep, init=1'b0 *) wire w;
+$_DFF_P_ ff(.C(clk), .D(d), .Q(w));
 assign q = w;
 endmodule
 EOT
-abc9 -lut 4 -dff
+equiv_opt -assert abc9 -lut 4 -dff
+design -load postopt
+cd abc9_test036
+select -assert-count 1 t:$_DFF_P_
+select -assert-none t:* t:$_DFF_P_ %d
 
 
 design -reset
@@ -67,8 +69,32 @@ specify
 endspecify
 endmodule
 
-module top(input [1:0] i, output o);
+module abc9_test037(input [1:0] i, output o);
 LUT2 #(.mask(4'b0)) lut (.i(i), .o(o));
 endmodule
 EOT
 abc9
+
+
+design -reset
+read_verilog -icells <<EOT
+module abc9_test038(input clk, output w, x, y, z);
+(* init=1'b1 *) wire w;
+$_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w));
+(* init=1'bx *) wire x;
+$_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x));
+(* init=1'b0 *) wire y;
+$_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y));
+(* init=1'b0 *) wire z;
+$_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z));
+endmodule
+EOT
+simplemap
+equiv_opt abc9 -lut 4 -dff
+design -load postopt
+cd abc9_test038
+select -assert-count 3 t:$_DFF_N_
+select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
+clean
+select -assert-count 2 a:init
+select -assert-none w:w w:z %% a:init %D
diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v
index f55ef2316..8c9fb2926 100644
--- a/tests/various/attrib07_func_call.v
+++ b/tests/various/attrib07_func_call.v
@@ -11,7 +11,7 @@ module foo(clk, rst, inp_a, inp_b, out);
   input  wire rst;
   input  wire [7:0] inp_a;
   input  wire [7:0] inp_b;
-  output wire [7:0] out;
+  output reg  [7:0] out;
 
   always @(posedge clk)
     if (rst) out <= 0;
diff --git a/tests/various/constmsk_testmap.v b/tests/various/constmsk_testmap.v
index fab1b1bbc..b6809c7c0 100644
--- a/tests/various/constmsk_testmap.v
+++ b/tests/various/constmsk_testmap.v
@@ -1,7 +1,7 @@
 (* techmap_celltype = "$reduce_or" *)
 module my_opt_reduce_or(...);
     parameter A_SIGNED = 0;
-    parameter A_WIDTH = 1;
+    parameter A_WIDTH = 2;
     parameter Y_WIDTH = 1;
 
     input [A_WIDTH-1:0] A;
diff --git a/tests/various/printattr.ys b/tests/various/printattr.ys
new file mode 100644
index 000000000..afc6d8eb6
--- /dev/null
+++ b/tests/various/printattr.ys
@@ -0,0 +1,14 @@
+logger -expect log ".*cells_not_processed=[01]* .*" 1
+logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
+read_verilog <<EOT
+module mux2(a, b, s, y);
+	input a, b, s;
+	output y;
+
+	wire s_n = ~s;
+	wire t0 = s & a;
+	wire t1 = s_n & b;
+	assign y = t0 | t1;
+endmodule
+EOT
+printattrs
diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
index 604c2c976..dc828eda7 100644
--- a/tests/various/shregmap.v
+++ b/tests/various/shregmap.v
@@ -13,7 +13,7 @@ assign q = {shift2[3], shift1[3]};
 endmodule
 
 module $__SHREG_DFF_P_(input C, D, output Q);
-parameter DEPTH = 1;
+parameter DEPTH = 2;
 parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
 reg [DEPTH-1:0] r = INIT;
 always @(posedge C) 
@@ -38,7 +38,7 @@ endmodule
 module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
 parameter CLKPOL = 1;
 parameter ENPOL = 1;
-parameter DEPTH = 1;
+parameter DEPTH = 2;
 parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
 reg [DEPTH-1:0] r = INIT;
 wire clk = C ^ CLKPOL;
diff --git a/tests/various/xaiger.ys b/tests/various/xaiger.ys
new file mode 100644
index 000000000..f612d2e18
--- /dev/null
+++ b/tests/various/xaiger.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top(input a, b, output c);
+bb #(1) bb();
+endmodule
+
+module bb(input a, b, output c);
+parameter p = 0;
+assign c = a ^ b;
+endmodule
+EOT
+blackbox bb
+hierarchy
+write_xaiger /dev/null
diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys
new file mode 100644
index 000000000..4b629ba92
--- /dev/null
+++ b/tests/verilog/bug2037.ys
@@ -0,0 +1,58 @@
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+	always @(*)
+		if (y) (* foo *) ;
+endmodule
+EOT
+select -assert-none a:* a:src %d
+
+
+design -reset
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+	always @(*)
+		if (y) (* foo *) ; else (* bar *) ;
+endmodule
+EOT
+select -assert-none a:* a:src %d
+
+
+design -reset
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+    generate if (y) (* foo *) ; endgenerate
+endmodule
+EOT
+select -assert-none a:*
+
+
+design -reset
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+    generate if (y) (* foo *) ; else (* bar *); endgenerate
+endmodule
+EOT
+select -assert-none a:*
+
+
+design -reset
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+	reg x = 1'b0;
+	always @(*) begin
+		if (y)
+			(* foo *) x <= 1'b1;
+		else
+			(* bar *) x = 1'b0;
+	end
+endmodule
+EOT
diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
index e815d7fc5..91989f412 100644
--- a/tests/verilog/bug2042-sv.ys
+++ b/tests/verilog/bug2042-sv.ys
@@ -2,7 +2,7 @@ read_verilog -sv <<EOT
 module Task_Test_Top
 (
 input a,
-output b
+output reg b
 );
 
     task SomeTaskName(a);
diff --git a/tests/verilog/task_attr.ys b/tests/verilog/task_attr.ys
new file mode 100644
index 000000000..d6e75f85f
--- /dev/null
+++ b/tests/verilog/task_attr.ys
@@ -0,0 +1,28 @@
+read_verilog <<EOT
+module top;
+    task foo;
+    endtask
+
+    always @*
+        (* foo *) foo;
+
+    initial
+        if (0) $info("bar");
+endmodule
+EOT
+# Since task enables are not an RTLIL object,
+#   any attributes on their AST get dropped
+select -assert-none a:* a:src %d
+
+
+logger -expect error "syntax error, unexpected ATTR_BEGIN" 1
+design -reset
+read_verilog <<EOT
+module top;
+    task foo;
+    endtask
+
+    always @*
+        foo (* foo *);
+endmodule
+EOT