4 files changed, 121 insertions, 0 deletions
diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index 0e353ad9b..dcd450e47 100644
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -159,3 +159,88 @@ generate
     end
 endgenerate
 endmodule
+
+// ------------------------------------------
+
+module gen_test7;
+	reg [2:0] out1;
+	reg [2:0] out2;
+	wire [2:0] out3;
+	generate
+		begin : cond
+			reg [2:0] sub_out1;
+			reg [2:0] sub_out2;
+			wire [2:0] sub_out3;
+			initial begin : init
+				reg signed [31:0] x;
+				x = 2 ** 2;
+				out1 = x;
+				sub_out1 = x;
+			end
+			always @* begin : proc
+				reg signed [31:0] x;
+				x = 2 ** 1;
+				out2 = x;
+				sub_out2 = x;
+			end
+			genvar x;
+			for (x = 0; x < 3; x = x + 1) begin
+				assign out3[x] = 1;
+				assign sub_out3[x] = 1;
+			end
+		end
+	endgenerate
+
+// `define VERIFY
+`ifdef VERIFY
+	assert property (out1 == 4);
+	assert property (out2 == 2);
+	assert property (out3 == 7);
+	assert property (cond.sub_out1 == 4);
+	assert property (cond.sub_out2 == 2);
+	assert property (cond.sub_out3 == 7);
+`endif
+endmodule
+
+// ------------------------------------------
+
+module gen_test8;
+
+// `define VERIFY
+`ifdef VERIFY
+	`define ASSERT(expr) assert property (expr);
+`else
+	`define ASSERT(expr)
+`endif
+
+	wire [1:0] x = 2'b11;
+	generate
+		begin : A
+			wire [1:0] x;
+			begin : B
+				wire [1:0] x = 2'b00;
+				`ASSERT(x == 0)
+				`ASSERT(A.x == 2)
+				`ASSERT(A.C.x == 1)
+				`ASSERT(A.B.x == 0)
+			end
+			begin : C
+				wire [1:0] x = 2'b01;
+				`ASSERT(x == 1)
+				`ASSERT(A.x == 2)
+				`ASSERT(A.C.x == 1)
+				`ASSERT(A.B.x == 0)
+			end
+			assign x = B.x ^ 2'b11 ^ C.x;
+			`ASSERT(x == 2)
+			`ASSERT(A.x == 2)
+			`ASSERT(A.C.x == 1)
+			`ASSERT(A.B.x == 0)
+		end
+	endgenerate
+
+	`ASSERT(x == 3)
+	`ASSERT(A.x == 2)
+	`ASSERT(A.C.x == 1)
+	`ASSERT(A.B.x == 0)
+endmodule
diff --git a/tests/various/const_func.v b/tests/various/const_func.v
index 76cdc385d..541e63b19 100644
--- a/tests/various/const_func.v
+++ b/tests/various/const_func.v
@@ -53,6 +53,15 @@ module top(out);
         c1, c2, c3, c4,
         d1, d2, d3, d4};
 
+    function signed [31:0] negate;
+        input integer inp;
+        negate = ~inp;
+    endfunction
+    parameter W = 10;
+    parameter X = 3;
+    localparam signed Y = $floor(W / X);
+    localparam signed Z = negate($floor(W / X));
+
 // `define VERIFY
 `ifdef VERIFY
     assert property (a1 == 0);
@@ -71,5 +80,8 @@ module top(out);
     assert property (d2 == 0);
     assert property (d3 == 1);
     assert property (d4 == 1);
+
+    assert property (Y == 3);
+    assert property (Z == ~3);
 `endif
 endmodule
diff --git a/tests/various/const_func_block_var.v b/tests/various/const_func_block_var.v
new file mode 100644
index 000000000..98e83aa5b
--- /dev/null
+++ b/tests/various/const_func_block_var.v
@@ -0,0 +1,23 @@
+module top(out);
+	function integer operation;
+		input integer num;
+		begin
+			operation = 0;
+			begin : op_i
+				integer i;
+				for (i = 0; i < 2; i = i + 1)
+				begin : op_j
+					integer j;
+					for (j = i; j < i * 2; j = j + 1)
+						num = num + 1;
+				end
+				num = num * 2;
+			end
+			operation = num;
+		end
+	endfunction
+
+	localparam res = operation(4);
+	output wire [31:0] out;
+	assign out = res;
+endmodule
diff --git a/tests/various/const_func_block_var.ys b/tests/various/const_func_block_var.ys
new file mode 100644
index 000000000..7c2e85c64
--- /dev/null
+++ b/tests/various/const_func_block_var.ys
@@ -0,0 +1 @@
+read_verilog const_func_block_var.v