diff options
Diffstat (limited to 'tests')
41 files changed, 921 insertions, 78 deletions
diff --git a/tests/arch/nexus/mul.ys b/tests/arch/nexus/mul.ys index 27ea3e04e..65a2fd8c3 100644 --- a/tests/arch/nexus/mul.ys +++ b/tests/arch/nexus/mul.ys @@ -1,4 +1,5 @@ read_verilog ../common/mul.v +chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 hierarchy -top top proc @@ -7,22 +8,43 @@ design -save read equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 7 t:CCU2 -select -assert-max 5 t:WIDEFN9 -select -assert-max 62 t:LUT4 +select -assert-count 1 t:MULT9X9 -select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT9X9 %% t:* %D -design -load read -equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_nexus +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18 +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X18 %% t:* %D + + +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_nexus cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X36 +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X36 %% t:* %D -stat -select -assert-count 7 t:CCU2 -select -assert-max 12 t:WIDEFN9 -select -assert-max 58 t:LUT4 +design -reset +read_verilog ../common/mul.v +chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64 +hierarchy -top top +proc +# equivalence checking is too slow here +synth_nexus +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT36X36 -select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D +select -assert-none t:IB t:OB t:VLO t:VHI t:MULT36X36 %% t:* %D diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 1b2788448..c2a23de6d 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -40,10 +40,11 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module +select -assert-max 2 t:LUT3 select -assert-max 2 t:LUT4 select -assert-min 4 t:LUT6 select -assert-max 7 t:LUT6 select -assert-max 2 t:MUXF7 dump -select -assert-none t:LUT6 t:LUT4 t:MUXF7 %% t:* %D +select -assert-none t:LUT6 t:LUT4 t:LUT3 t:MUXF7 %% t:* %D diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys index 2c729832e..c09699411 100644 --- a/tests/arch/xilinx/xilinx_dffopt.ys +++ b/tests/arch/xilinx/xilinx_dffopt.ys @@ -223,3 +223,49 @@ select -assert-count 1 t:LUT2 select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D design -reset + + +read_verilog << EOT + +// FDSE_1, mergeable CE and S, but CE only not worth it. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); + +FDSE_1 ff (.D(tmp[0]), .CE(i[7]), .S(tmp[1]), .Q(o[0])); + +endmodule + +EOT + +read_verilog -lib +/xilinx/cells_sim.v +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +cd t0 +select -assert-count 1 t:FDSE_1 +select -assert-count 1 t:LUT5 +select -assert-none t:FDSE_1 t:LUT5 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +cd t0 +select -assert-count 1 t:FDSE_1 +select -assert-count 2 t:LUT2 +select -assert-none t:FDSE_1 t:LUT2 %% t:* %D + +design -reset diff --git a/tests/opt/opt_share_bug2538.ys b/tests/opt/opt_share_bug2538.ys new file mode 100644 index 000000000..7261c6695 --- /dev/null +++ b/tests/opt/opt_share_bug2538.ys @@ -0,0 +1,20 @@ +read_verilog <<EOT + +module top(...); + +input [3:0] A; +input S; +output [1:0] Y; + +wire [3:0] A1 = A + 1; +wire [3:0] A2 = A + 2; +assign Y = S ? A1[3:2] : A2[3:2]; + +endmodule + +EOT + +proc +alumacc +equiv_opt -assert opt_share + diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv new file mode 100644 index 000000000..75c4cd136 --- /dev/null +++ b/tests/simple/macro_arg_spaces.sv @@ -0,0 +1,28 @@ +module top( + input wire [31:0] i, + output wire [31:0] x, y, z +); + +`define BAR(a) a +`define FOO(a = function automatic [31:0] f) a + +`BAR(function automatic [31:0] a); + input [31:0] i; + a = i * 2; +endfunction + +`FOO(); + input [31:0] i; + f = i * 3; +endfunction + +`FOO(function automatic [31:0] b); + input [31:0] i; + b = i * 5; +endfunction + +assign x = a(i); +assign y = f(i); +assign z = b(i); + +endmodule diff --git a/tests/simple/macro_arg_surrounding_spaces.v b/tests/simple/macro_arg_surrounding_spaces.v new file mode 100644 index 000000000..3dbb5ea01 --- /dev/null +++ b/tests/simple/macro_arg_surrounding_spaces.v @@ -0,0 +1,20 @@ +module top( + IDENT_V_, + IDENT_W_, + IDENT_X_, + IDENT_Y_, + IDENT_Z_, + IDENT_A_, + IDENT_B_, + IDENT_C_ +); + `define MACRO(dummy, x) IDENT_``x``_ + output wire IDENT_V_; + output wire `MACRO(_,W); + output wire `MACRO(_, X); + output wire `MACRO(_,Y ); + output wire `MACRO(_, Z ); + output wire `MACRO(_, A); + output wire `MACRO(_,B ); + output wire `MACRO(_, C ); +endmodule diff --git a/tests/svtypes/typedef_struct_port.sv b/tests/svtypes/typedef_struct_port.sv new file mode 100644 index 000000000..ecc03bee8 --- /dev/null +++ b/tests/svtypes/typedef_struct_port.sv @@ -0,0 +1,111 @@ +package p; + +typedef struct packed { + byte a; + byte b; +} p_t; + +typedef logic [31:0] l_t; + +endpackage + +module foo1( + input p::p_t p, + output p::p_t o +); + assign o = p; +endmodule + +module foo2(p, o); + input p::p_t p; + output p::p_t o; + assign o = p; +endmodule + +module foo3(input p::l_t p, input p::l_t o); + assign o = p; +endmodule + +module foo4(input logic [15:0] p, input logic [15:0] o); + assign o = p; +endmodule + +module test_parser(a,b,c,d,e,f,g,h,i); +input [7:0] a; // no explicit net declaration - net is unsigned +input [7:0] b; +input signed [7:0] c; +input signed [7:0] d; // no explicit net declaration - net is signed +output [7:0] e; // no explicit net declaration - net is unsigned +output [7:0] f; +output signed [7:0] g; +output signed [7:0] h; // no explicit net declaration - net is signed +output unsigned [7:0] i; +wire signed [7:0] b; // port b inherits signed attribute from net decl. +wire [7:0] c; // net c inherits signed attribute from port +logic signed [7:0] f;// port f inherits signed attribute from logic decl. +logic [7:0] g; // logic g inherits signed attribute from port + + assign a = 8'b10001111; + assign b = 8'b10001111; + assign c = 8'b10001111; + assign d = 8'b10001111; + assign e = 8'b10001111; + assign f = 8'b10001111; + assign g = 8'b10001111; + assign h = 8'b10001111; + assign i = 8'b10001111; + always_comb begin + assert($unsigned(143) == a); + assert($signed(-113) == b); + assert($signed(-113) == c); + assert($signed(-113) == d); + assert($unsigned(143) == e); + assert($unsigned(143) == f); + assert($signed(-113) == g); + assert($signed(-113) == h); + assert($unsigned(143) == i); + end +endmodule + +module top; + p::p_t ps; + assign ps.a = 8'hAA; + assign ps.b = 8'h55; + foo1 foo(.p(ps)); + + p::p_t body; + assign body.a = 8'hBB; + assign body.b = 8'h66; + foo2 foo_b(.p(body)); + + typedef p::l_t local_alias; + + local_alias l_s; + assign l_s = 32'hAAAAAAAA; + foo3 foo_l(.p(l_s)); + + typedef logic [15:0] sl_t; + + sl_t sl_s; + assign sl_s = 16'hBBBB; + foo4 foo_sl(.p(sl_s)); + + typedef sl_t local_alias_st; + + local_alias_st lsl_s; + assign lsl_s = 16'hCCCC; + foo4 foo_lsl(.p(lsl_s)); + + const logic j = 1'b1; + + always_comb begin + assert(8'hAA == ps.a); + assert(8'h55 == ps.b); + assert(8'hBB == body.a); + assert(8'h66 == body.b); + assert(32'hAAAAAAAA == l_s); + assert(16'hBBBB == sl_s); + assert(16'hCCCC == lsl_s); + assert(1'b1 == j); + end +endmodule diff --git a/tests/svtypes/typedef_struct_port.ys b/tests/svtypes/typedef_struct_port.ys new file mode 100644 index 000000000..5b75c3105 --- /dev/null +++ b/tests/svtypes/typedef_struct_port.ys @@ -0,0 +1,6 @@ +read_verilog -sv typedef_struct_port.sv +hierarchy; proc; opt +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all +select -module test_parser +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 12d4e5048..2bb6c7179 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -4,3 +4,4 @@ /write_gzip.v.gz /run-test.mk /plugin.so +/plugin.so.dSYM diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v index 3bfff4acd..358fb439a 100644 --- a/tests/various/const_arg_loop.v +++ b/tests/various/const_arg_loop.v @@ -14,6 +14,11 @@ module top; end endfunction + function automatic [31:0] pass_through; + input [31:0] inp; + pass_through = inp; + endfunction + function automatic [31:0] operation2; input [4:0] var; input integer num; @@ -39,6 +44,18 @@ module top; end endfunction + function automatic [16:0] operation4; + input [15:0] a; + input b; + operation4 = {a, b}; + endfunction + + function automatic integer operation5; + input x; + integer x; + operation5 = x; + endfunction + wire [31:0] a; assign a = 2; @@ -47,18 +64,30 @@ module top; wire [31:0] x1; assign x1 = operation1(A, a); + wire [31:0] x1b; + assign x1b = operation1(pass_through(A), a); + wire [31:0] x2; assign x2 = operation2(A, a); wire [31:0] x3; assign x3 = operation3(A, a); + wire [16:0] x4; + assign x4 = operation4(a[15:0], 0); + + wire [31:0] x5; + assign x5 = operation5(64); + // `define VERIFY `ifdef VERIFY assert property (a == 2); assert property (A == 3); assert property (x1 == 16); + assert property (x1b == 16); assert property (x2 == 4); assert property (x3 == 16); + assert property (x4 == a << 1); + assert property (x5 == 64); `endif endmodule diff --git a/tests/various/dynamic_part_select.ys b/tests/various/dynamic_part_select.ys index abc1daad6..2dc061e89 100644 --- a/tests/various/dynamic_part_select.ys +++ b/tests/various/dynamic_part_select.ys @@ -21,18 +21,18 @@ read_verilog ./dynamic_part_select/multiple_blocking.v proc rename -top gold design -stash gold - + read_verilog ./dynamic_part_select/multiple_blocking_gate.v proc rename -top gate design -stash gate - + design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv - + ### Non-blocking to the same output register ### design -reset read_verilog ./dynamic_part_select/nonblocking.v @@ -44,13 +44,13 @@ read_verilog ./dynamic_part_select/nonblocking_gate.v proc rename -top gate design -stash gate - + design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv - + ### For-loop select, one dynamic input design -reset read_verilog ./dynamic_part_select/forloop_select.v @@ -62,13 +62,13 @@ read_verilog ./dynamic_part_select/forloop_select_gate.v proc rename -top gate design -stash gate - + design -copy-from gold -as gold gold design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv - + #### Double loop (part-select, reset) ### design -reset read_verilog ./dynamic_part_select/reset_test.v @@ -83,10 +83,10 @@ design -stash gate design -copy-from gold -as gold gold design -copy-from gate -as gate gate - + miter -equiv -make_assert -make_outcmp -flatten gold gate equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv - + ### Reversed part-select case ### design -reset read_verilog ./dynamic_part_select/reversed.v @@ -101,6 +101,62 @@ design -stash gate design -copy-from gold -as gold gold design -copy-from gate -as gate gate - + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv + +### Latches +## Issue 1990 +design -reset +read_verilog ./dynamic_part_select/latch_1990.v +hierarchy -top latch_1990; prep; async2sync +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/latch_1990_gate.v +hierarchy -top latch_1990_gate; prep +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +sat -prove-asserts -show-public -verify -set-init-zero equiv + +### +## Part select with obvious latch, expected to fail due comparison with old shift&mask AST transformation +design -reset +read_verilog ./dynamic_part_select/latch_002.v +hierarchy -top latch_002; prep; async2sync +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/latch_002_gate.v +hierarchy -top latch_002_gate; prep; async2sync +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +sat -prove-asserts -seq 10 -show-public -falsify -set-init-zero equiv + +## Part select + latch, with no shift&mask +design -reset +read_verilog ./dynamic_part_select/latch_002.v +hierarchy -top latch_002; prep; async2sync +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/latch_002_gate_good.v +hierarchy -top latch_002_gate; prep; async2sync +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + miter -equiv -make_assert -make_outcmp -flatten gold gate equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv diff --git a/tests/various/dynamic_part_select/forloop_select.v b/tests/various/dynamic_part_select/forloop_select.v index 8260f3186..926fb3133 100644 --- a/tests/various/dynamic_part_select/forloop_select.v +++ b/tests/various/dynamic_part_select/forloop_select.v @@ -1,13 +1,14 @@ +`default_nettype none module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW) - (input clk, - input [CTRLW-1:0] ctrl, - input [DINW-1:0] din, - input en, + (input wire clk, + input wire [CTRLW-1:0] ctrl, + input wire [DINW-1:0] din, + input wire en, output reg [WIDTH-1:0] dout); - - reg [SELW:0] sel; + + reg [SELW:0] sel; localparam SLICE = WIDTH/(SELW**2); - + always @(posedge clk) begin if (en) begin @@ -16,4 +17,3 @@ module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2* end end endmodule - diff --git a/tests/various/dynamic_part_select/forloop_select_gate.v b/tests/various/dynamic_part_select/forloop_select_gate.v index 71ae88537..1a5fffdc7 100644 --- a/tests/various/dynamic_part_select/forloop_select_gate.v +++ b/tests/various/dynamic_part_select/forloop_select_gate.v @@ -1,8 +1,9 @@ +`default_nettype none module forloop_select_gate (clk, ctrl, din, en, dout); - input clk; - input [3:0] ctrl; - input [15:0] din; - input en; + input wire clk; + input wire [3:0] ctrl; + input wire [15:0] din; + input wire en; output reg [15:0] dout; reg [4:0] sel; always @(posedge clk) diff --git a/tests/various/dynamic_part_select/latch_002.v b/tests/various/dynamic_part_select/latch_002.v new file mode 100644 index 000000000..7617d6a72 --- /dev/null +++ b/tests/various/dynamic_part_select/latch_002.v @@ -0,0 +1,13 @@ +`default_nettype none +module latch_002 + (dword, sel, st, vect); + output reg [63:0] dword; + input wire [7:0] vect; + input wire [7:0] sel; + input wire st; + + always @(*) begin + if (st) + dword[8*sel +:8] <= vect[7:0]; + end +endmodule // latch_002 diff --git a/tests/various/dynamic_part_select/latch_002_gate.v b/tests/various/dynamic_part_select/latch_002_gate.v new file mode 100644 index 000000000..4acf129c6 --- /dev/null +++ b/tests/various/dynamic_part_select/latch_002_gate.v @@ -0,0 +1,18 @@ +`default_nettype none +module latch_002_gate(dword, vect, sel, st); + output reg [63:0] dword; + input wire [7:0] vect; + input wire [7:0] sel; + input wire st; + reg [63:0] mask; + reg [63:0] data; + always @* + case (|(st)) + 1'b 1: + begin + mask = (8'b 11111111)<<((((8)*(sel)))+(0)); + data = ((8'b 11111111)&(vect[7:0]))<<((((8)*(sel)))+(0)); + dword <= ((dword)&(~(mask)))|(data); + end + endcase +endmodule diff --git a/tests/various/dynamic_part_select/latch_002_gate_good.v b/tests/various/dynamic_part_select/latch_002_gate_good.v new file mode 100644 index 000000000..809c74fc9 --- /dev/null +++ b/tests/various/dynamic_part_select/latch_002_gate_good.v @@ -0,0 +1,141 @@ +`default_nettype none +module latch_002_gate (dword, vect, sel, st); + output reg [63:0] dword; + input wire [7:0] vect; + input wire [7:0] sel; + input st; + always @* + case (|(st)) + 1'b 1: + case ((((8)*(sel)))+(0)) + 0: + dword[7:0] <= vect[7:0]; + 1: + dword[8:1] <= vect[7:0]; + 2: + dword[9:2] <= vect[7:0]; + 3: + dword[10:3] <= vect[7:0]; + 4: + dword[11:4] <= vect[7:0]; + 5: + dword[12:5] <= vect[7:0]; + 6: + dword[13:6] <= vect[7:0]; + 7: + dword[14:7] <= vect[7:0]; + 8: + dword[15:8] <= vect[7:0]; + 9: + dword[16:9] <= vect[7:0]; + 10: + dword[17:10] <= vect[7:0]; + 11: + dword[18:11] <= vect[7:0]; + 12: + dword[19:12] <= vect[7:0]; + 13: + dword[20:13] <= vect[7:0]; + 14: + dword[21:14] <= vect[7:0]; + 15: + dword[22:15] <= vect[7:0]; + 16: + dword[23:16] <= vect[7:0]; + 17: + dword[24:17] <= vect[7:0]; + 18: + dword[25:18] <= vect[7:0]; + 19: + dword[26:19] <= vect[7:0]; + 20: + dword[27:20] <= vect[7:0]; + 21: + dword[28:21] <= vect[7:0]; + 22: + dword[29:22] <= vect[7:0]; + 23: + dword[30:23] <= vect[7:0]; + 24: + dword[31:24] <= vect[7:0]; + 25: + dword[32:25] <= vect[7:0]; + 26: + dword[33:26] <= vect[7:0]; + 27: + dword[34:27] <= vect[7:0]; + 28: + dword[35:28] <= vect[7:0]; + 29: + dword[36:29] <= vect[7:0]; + 30: + dword[37:30] <= vect[7:0]; + 31: + dword[38:31] <= vect[7:0]; + 32: + dword[39:32] <= vect[7:0]; + 33: + dword[40:33] <= vect[7:0]; + 34: + dword[41:34] <= vect[7:0]; + 35: + dword[42:35] <= vect[7:0]; + 36: + dword[43:36] <= vect[7:0]; + 37: + dword[44:37] <= vect[7:0]; + 38: + dword[45:38] <= vect[7:0]; + 39: + dword[46:39] <= vect[7:0]; + 40: + dword[47:40] <= vect[7:0]; + 41: + dword[48:41] <= vect[7:0]; + 42: + dword[49:42] <= vect[7:0]; + 43: + dword[50:43] <= vect[7:0]; + 44: + dword[51:44] <= vect[7:0]; + 45: + dword[52:45] <= vect[7:0]; + 46: + dword[53:46] <= vect[7:0]; + 47: + dword[54:47] <= vect[7:0]; + 48: + dword[55:48] <= vect[7:0]; + 49: + dword[56:49] <= vect[7:0]; + 50: + dword[57:50] <= vect[7:0]; + 51: + dword[58:51] <= vect[7:0]; + 52: + dword[59:52] <= vect[7:0]; + 53: + dword[60:53] <= vect[7:0]; + 54: + dword[61:54] <= vect[7:0]; + 55: + dword[62:55] <= vect[7:0]; + 56: + dword[63:56] <= vect[7:0]; + 57: + dword[63:57] <= vect[7:0]; + 58: + dword[63:58] <= vect[7:0]; + 59: + dword[63:59] <= vect[7:0]; + 60: + dword[63:60] <= vect[7:0]; + 61: + dword[63:61] <= vect[7:0]; + 62: + dword[63:62] <= vect[7:0]; + 63: + dword[63:63] <= vect[7:0]; + endcase + endcase +endmodule diff --git a/tests/various/dynamic_part_select/latch_1990.v b/tests/various/dynamic_part_select/latch_1990.v new file mode 100644 index 000000000..864c05244 --- /dev/null +++ b/tests/various/dynamic_part_select/latch_1990.v @@ -0,0 +1,12 @@ +module latch_1990 #( + parameter BUG = 1 +) ( + (* nowrshmsk = !BUG *) + output reg [1:0] x +); + wire z = 0; + integer i; + always @* + for (i = 0; i < 2; i=i+1) + x[z^i] = z^i; +endmodule diff --git a/tests/various/dynamic_part_select/latch_1990_gate.v b/tests/various/dynamic_part_select/latch_1990_gate.v new file mode 100644 index 000000000..a46183f23 --- /dev/null +++ b/tests/various/dynamic_part_select/latch_1990_gate.v @@ -0,0 +1,6 @@ +`default_nettype none +module latch_1990_gate + (output wire [1:0] x); + assign x = 2'b10; +endmodule // latch_1990_gate + diff --git a/tests/various/dynamic_part_select/multiple_blocking.v b/tests/various/dynamic_part_select/multiple_blocking.v index 2858f7741..3bb249a76 100644 --- a/tests/various/dynamic_part_select/multiple_blocking.v +++ b/tests/various/dynamic_part_select/multiple_blocking.v @@ -1,8 +1,9 @@ +`default_nettype none module multiple_blocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) - (input clk, - input [CTRLW-1:0] ctrl, - input [DINW-1:0] din, - input [SELW-1:0] sel, + (input wire clk, + input wire [CTRLW-1:0] ctrl, + input wire [DINW-1:0] din, + input wire [SELW-1:0] sel, output reg [WIDTH-1:0] dout); localparam SLICE = WIDTH/(SELW**2); diff --git a/tests/various/dynamic_part_select/multiple_blocking_gate.v b/tests/various/dynamic_part_select/multiple_blocking_gate.v index 073b559dc..840918876 100644 --- a/tests/various/dynamic_part_select/multiple_blocking_gate.v +++ b/tests/various/dynamic_part_select/multiple_blocking_gate.v @@ -1,8 +1,9 @@ +`default_nettype none module multiple_blocking_gate (clk, ctrl, din, sel, dout); - input clk; - input [4:0] ctrl; - input [1:0] din; - input [0:0] sel; + input wire clk; + input wire [4:0] ctrl; + input wire [1:0] din; + input wire [0:0] sel; output reg [31:0] dout; reg [5:0] a; reg [0:0] b; diff --git a/tests/various/dynamic_part_select/nonblocking.v b/tests/various/dynamic_part_select/nonblocking.v index 0949b31a9..20f857cf9 100644 --- a/tests/various/dynamic_part_select/nonblocking.v +++ b/tests/various/dynamic_part_select/nonblocking.v @@ -1,8 +1,9 @@ +`default_nettype none module nonblocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) - (input clk, - input [CTRLW-1:0] ctrl, - input [DINW-1:0] din, - input [SELW-1:0] sel, + (input wire clk, + input wire [CTRLW-1:0] ctrl, + input wire [DINW-1:0] din, + input wire [SELW-1:0] sel, output reg [WIDTH-1:0] dout); localparam SLICE = WIDTH/(SELW**2); diff --git a/tests/various/dynamic_part_select/nonblocking_gate.v b/tests/various/dynamic_part_select/nonblocking_gate.v index ed1ee2776..212d44609 100644 --- a/tests/various/dynamic_part_select/nonblocking_gate.v +++ b/tests/various/dynamic_part_select/nonblocking_gate.v @@ -1,8 +1,9 @@ +`default_nettype none module nonblocking_gate (clk, ctrl, din, sel, dout); - input clk; - input [4:0] ctrl; - input [1:0] din; - input [0:0] sel; + input wire clk; + input wire [4:0] ctrl; + input wire [1:0] din; + input wire [0:0] sel; output reg [31:0] dout; always @(posedge clk) begin diff --git a/tests/various/dynamic_part_select/original.v b/tests/various/dynamic_part_select/original.v index f7dfed1a1..41310a215 100644 --- a/tests/various/dynamic_part_select/original.v +++ b/tests/various/dynamic_part_select/original.v @@ -1,8 +1,9 @@ +`default_nettype none module original #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) - (input clk, - input [CTRLW-1:0] ctrl, - input [DINW-1:0] din, - input [SELW-1:0] sel, + (input wire clk, + input wire [CTRLW-1:0] ctrl, + input wire [DINW-1:0] din, + input wire [SELW-1:0] sel, output reg [WIDTH-1:0] dout); localparam SLICE = WIDTH/(SELW**2); always @(posedge clk) diff --git a/tests/various/dynamic_part_select/original_gate.v b/tests/various/dynamic_part_select/original_gate.v index 22093bf63..963b4228c 100644 --- a/tests/various/dynamic_part_select/original_gate.v +++ b/tests/various/dynamic_part_select/original_gate.v @@ -1,8 +1,9 @@ +`default_nettype none module original_gate (clk, ctrl, din, sel, dout); - input clk; - input [4:0] ctrl; - input [1:0] din; - input [0:0] sel; + input wire clk; + input wire [4:0] ctrl; + input wire [1:0] din; + input wire [0:0] sel; output reg [31:0] dout; always @(posedge clk) case (({(ctrl)*(sel)})+(0)) diff --git a/tests/various/dynamic_part_select/reset_test.v b/tests/various/dynamic_part_select/reset_test.v index 29355aafb..1bb9379f2 100644 --- a/tests/various/dynamic_part_select/reset_test.v +++ b/tests/various/dynamic_part_select/reset_test.v @@ -1,8 +1,10 @@ +`default_nettype none module reset_test #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW) - (input clk, - input [CTRLW-1:0] ctrl, - input [DINW-1:0] din, - input [SELW-1:0] sel, + (input wire clk, + input wire reset, + input wire [CTRLW-1:0] ctrl, + input wire [DINW-1:0] din, + input wire [SELW-1:0] sel, output reg [WIDTH-1:0] dout); reg [SELW:0] i; @@ -16,8 +18,6 @@ module reset_test #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SE dout[i*rval+:SLICE] <= 32'hDEAD; end end - //else begin dout[ctrl*sel+:SLICE] <= din; - //end end endmodule diff --git a/tests/various/dynamic_part_select/reset_test_gate.v b/tests/various/dynamic_part_select/reset_test_gate.v index 96dff4135..4ae76c4f7 100644 --- a/tests/various/dynamic_part_select/reset_test_gate.v +++ b/tests/various/dynamic_part_select/reset_test_gate.v @@ -1,8 +1,10 @@ -module reset_test_gate (clk, ctrl, din, sel, dout); - input clk; - input [4:0] ctrl; - input [1:0] din; - input [0:0] sel; +`default_nettype none +module reset_test_gate (clk, reset, ctrl, din, sel, dout); + input wire clk; + input wire reset; + input wire [4:0] ctrl; + input wire [1:0] din; + input wire [0:0] sel; output reg [31:0] dout; reg [1:0] i; wire [0:0] rval; diff --git a/tests/various/dynamic_part_select/reversed.v b/tests/various/dynamic_part_select/reversed.v index 8b114ac77..0268fa6bb 100644 --- a/tests/various/dynamic_part_select/reversed.v +++ b/tests/various/dynamic_part_select/reversed.v @@ -1,8 +1,9 @@ +`default_nettype none module reversed #(parameter WIDTH=32, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW) - (input clk, - input [CTRLW-1:0] ctrl, - input [DINW-1:0] din, - input [SELW-1:0] sel, + (input wire clk, + input wire [CTRLW-1:0] ctrl, + input wire [DINW-1:0] din, + input wire [SELW-1:0] sel, output reg [WIDTH-1:0] dout); localparam SLICE = WIDTH/(SELW**2); diff --git a/tests/various/dynamic_part_select/reversed_gate.v b/tests/various/dynamic_part_select/reversed_gate.v index 9349d45ee..5ffdcb4d7 100644 --- a/tests/various/dynamic_part_select/reversed_gate.v +++ b/tests/various/dynamic_part_select/reversed_gate.v @@ -1,8 +1,9 @@ +`default_nettype none module reversed_gate (clk, ctrl, din, sel, dout); - input clk; - input [4:0] ctrl; - input [15:0] din; - input [3:0] sel; + input wire clk; + input wire [4:0] ctrl; + input wire [15:0] din; + input wire [3:0] sel; output reg [31:0] dout; always @(posedge clk) case ((({(32)-((ctrl)*(sel))})+(1))-(2)) diff --git a/tests/various/fib.v b/tests/various/fib.v new file mode 100644 index 000000000..986749626 --- /dev/null +++ b/tests/various/fib.v @@ -0,0 +1,65 @@ +module gate( + off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9 +); + input wire signed [31:0] off; + + function automatic integer fib( + input integer k + ); + if (k == 0) + fib = 0; + else if (k == 1) + fib = 1; + else + fib = fib(k - 1) + fib(k - 2); + endfunction + + function automatic integer fib_wrap( + input integer k, + output integer o + ); + o = off + fib(k); + endfunction + + output integer fib0; + output integer fib1; + output integer fib2; + output integer fib3; + output integer fib4; + output integer fib5; + output integer fib6; + output integer fib7; + output integer fib8; + output integer fib9; + + initial begin : blk + integer unused; + unused = fib_wrap(0, fib0); + unused = fib_wrap(1, fib1); + unused = fib_wrap(2, fib2); + unused = fib_wrap(3, fib3); + unused = fib_wrap(4, fib4); + unused = fib_wrap(5, fib5); + unused = fib_wrap(6, fib6); + unused = fib_wrap(7, fib7); + unused = fib_wrap(8, fib8); + unused = fib_wrap(9, fib9); + end +endmodule + +module gold( + off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9 +); + input wire signed [31:0] off; + + output integer fib0 = off + 0; + output integer fib1 = off + 1; + output integer fib2 = off + 1; + output integer fib3 = off + 2; + output integer fib4 = off + 3; + output integer fib5 = off + 5; + output integer fib6 = off + 8; + output integer fib7 = off + 13; + output integer fib8 = off + 21; + output integer fib9 = off + 34; +endmodule diff --git a/tests/various/fib.ys b/tests/various/fib.ys new file mode 100644 index 000000000..946e0738a --- /dev/null +++ b/tests/various/fib.ys @@ -0,0 +1,6 @@ +read_verilog fib.v +hierarchy +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/various/func_port_implied_dir.sv b/tests/various/func_port_implied_dir.sv new file mode 100644 index 000000000..0424f1b46 --- /dev/null +++ b/tests/various/func_port_implied_dir.sv @@ -0,0 +1,23 @@ +module gate(w, x, y, z); + function automatic integer bar( + integer a + ); + bar = 2 ** a; + endfunction + output integer w = bar(4); + + function automatic integer foo( + input integer a, /* implicitly input */ integer b, + output integer c, /* implicitly output */ integer d + ); + c = 42; + d = 51; + foo = a + b + 1; + endfunction + output integer x, y, z; + initial x = foo(1, 2, y, z); +endmodule + +module gold(w, x, y, z); + output integer w = 16, x = 4, y = 42, z = 51; +endmodule diff --git a/tests/various/func_port_implied_dir.ys b/tests/various/func_port_implied_dir.ys new file mode 100644 index 000000000..b5c22a05b --- /dev/null +++ b/tests/various/func_port_implied_dir.ys @@ -0,0 +1,6 @@ +read_verilog -sv func_port_implied_dir.sv +hierarchy +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/various/memory_word_as_index.data b/tests/various/memory_word_as_index.data new file mode 100644 index 000000000..d525c18ee --- /dev/null +++ b/tests/various/memory_word_as_index.data @@ -0,0 +1,4 @@ +00 04 08 0c +10 14 18 1c +20 24 28 2c +30 34 38 3c diff --git a/tests/various/memory_word_as_index.v b/tests/various/memory_word_as_index.v new file mode 100644 index 000000000..a99ea9566 --- /dev/null +++ b/tests/various/memory_word_as_index.v @@ -0,0 +1,21 @@ +`define DATA 64'h492e5c4d7747e032 + +`define GATE(n, expr) \ +module gate``n(sel, out); \ + input wire [3:0] sel; \ + output wire out; \ + reg [63:0] bits; \ + reg [5:0] ptrs[15:0]; \ + initial bits = `DATA; \ + initial $readmemh("memory_word_as_index.data", ptrs); \ + assign out = expr; \ +endmodule + +`GATE(1, bits[ptrs[sel]]) +`GATE(2, bits[ptrs[sel][5:0]]) +`GATE(3, bits[ptrs[sel]+:1]) + +module gold(sel, out); + input wire [3:0] sel; + output wire out = `DATA >> (sel * 4); +endmodule diff --git a/tests/various/memory_word_as_index.ys b/tests/various/memory_word_as_index.ys new file mode 100644 index 000000000..9a2dea40e --- /dev/null +++ b/tests/various/memory_word_as_index.ys @@ -0,0 +1,23 @@ +read_verilog memory_word_as_index.v + +hierarchy +proc +memory +flatten +opt -full + +equiv_make gold gate1 equiv +equiv_simple +equiv_status -assert + +delete equiv + +equiv_make gold gate2 equiv +equiv_simple +equiv_status -assert + +delete equiv + +equiv_make gold gate3 equiv +equiv_simple +equiv_status -assert diff --git a/tests/various/port_sign_extend.v b/tests/various/port_sign_extend.v new file mode 100644 index 000000000..446268268 --- /dev/null +++ b/tests/various/port_sign_extend.v @@ -0,0 +1,81 @@ +module GeneratorSigned1(out); + output wire signed out; + assign out = 1; +endmodule + +module GeneratorUnsigned1(out); + output wire out; + assign out = 1; +endmodule + +module GeneratorSigned2(out); + output wire signed [1:0] out; + assign out = 2; +endmodule + +module GeneratorUnsigned2(out); + output wire [1:0] out; + assign out = 2; +endmodule + +module PassThrough(a, b); + input wire [3:0] a; + output wire [3:0] b; + assign b = a; +endmodule + +module act(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2); + output wire [3:0] o1, o2, o3, o4, o5, o6; + + // unsigned constant + PassThrough pt1(1'b1, o1); + + // unsigned wire + wire tmp2; + assign tmp2 = 1'sb1; + PassThrough pt2(tmp2, o2); + + // signed constant + PassThrough pt3(1'sb1, o3); + + // signed wire + wire signed tmp4; + assign tmp4 = 1'sb1; + PassThrough pt4(tmp4, o4); + + // signed expressions + wire signed [1:0] tmp5a = 2'b11; + wire signed [1:0] tmp5b = 2'b01; + PassThrough pt5(tmp5a ^ tmp5b, o5); + + wire signed [2:0] tmp6a = 3'b100; + wire signed [2:0] tmp6b = 3'b001; + PassThrough pt6(tmp6a ? tmp6a : tmp6b, o6); + + output wire [2:0] yay1, nay1; + GeneratorSigned1 os1(yay1); + GeneratorUnsigned1 ou1(nay1); + + output wire [2:0] yay2, nay2; + GeneratorSigned2 os2(yay2); + GeneratorUnsigned2 ou2(nay2); +endmodule + +module ref(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2); + output wire [3:0] o1, o2, o3, o4, o5, o6; + + assign o1 = 4'b0001; + assign o2 = 4'b0001; + assign o3 = 4'b1111; + assign o4 = 4'b1111; + assign o5 = 4'b1110; + assign o6 = 4'b1100; + + output wire [2:0] yay1, nay1; + assign yay1 = 3'b111; + assign nay1 = 3'b001; + + output wire [2:0] yay2, nay2; + assign yay2 = 3'b110; + assign nay2 = 3'b010; +endmodule diff --git a/tests/various/port_sign_extend.ys b/tests/various/port_sign_extend.ys new file mode 100644 index 000000000..0a6a93810 --- /dev/null +++ b/tests/various/port_sign_extend.ys @@ -0,0 +1,22 @@ +read_verilog port_sign_extend.v +hierarchy +flatten +equiv_make ref act equiv +equiv_simple +equiv_status -assert + +delete + +read_verilog port_sign_extend.v +flatten +equiv_make ref act equiv +equiv_simple +equiv_status -assert + +delete + +read_verilog port_sign_extend.v +hierarchy +equiv_make ref act equiv +prep -flatten -top equiv +equiv_status -assert diff --git a/tests/various/rand_const.sv b/tests/various/rand_const.sv new file mode 100644 index 000000000..be00812c0 --- /dev/null +++ b/tests/various/rand_const.sv @@ -0,0 +1,8 @@ +module top; + rand const reg rx; + const reg ry; + rand reg rz; + rand const integer ix; + const integer iy; + rand integer iz; +endmodule diff --git a/tests/various/rand_const.ys b/tests/various/rand_const.ys new file mode 100644 index 000000000..74e43c7cc --- /dev/null +++ b/tests/various/rand_const.ys @@ -0,0 +1 @@ +read_verilog -sv rand_const.sv diff --git a/tests/verilog/wire_and_var.sv b/tests/verilog/wire_and_var.sv new file mode 100644 index 000000000..79c7c04c6 --- /dev/null +++ b/tests/verilog/wire_and_var.sv @@ -0,0 +1,33 @@ +`define TEST(kwd) \ + kwd kwd``_1; \ + kwd kwd``_2; \ + initial kwd``_1 = 1; \ + assign kwd``_2 = 1; + +`define TEST_VAR(kwd) \ + var kwd var_``kwd``_1; \ + var kwd var_``kwd``_2; \ + initial var_``kwd``_1 = 1; \ + assign var_``kwd``_2 = 1; + +`define TEST_WIRE(kwd) \ + wire kwd wire_``kwd``_1; \ + wire kwd wire_``kwd``_2; \ + initial wire_``kwd``_1 = 1; \ + assign wire_``kwd``_2 = 1; + +module top; + +`TEST(wire) // wire assigned in a block +`TEST(reg) // reg assigned in a continuous assignment +`TEST(logic) +`TEST(integer) + +`TEST_VAR(reg) // reg assigned in a continuous assignment +`TEST_VAR(logic) +`TEST_VAR(integer) + +`TEST_WIRE(logic) // wire assigned in a block +`TEST_WIRE(integer) // wire assigned in a block + +endmodule diff --git a/tests/verilog/wire_and_var.ys b/tests/verilog/wire_and_var.ys new file mode 100644 index 000000000..9359a9d55 --- /dev/null +++ b/tests/verilog/wire_and_var.ys @@ -0,0 +1,9 @@ +logger -expect warning "wire '\\wire_1' is assigned in a block" 1 +logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1 + +logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1 + +logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1 +logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1 + +read_verilog -sv wire_and_var.sv |