diff options
Diffstat (limited to 'tests')
83 files changed, 1997 insertions, 58 deletions
diff --git a/tests/arch/machxo2/.gitignore b/tests/arch/machxo2/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/arch/machxo2/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/arch/machxo2/add_sub.ys b/tests/arch/machxo2/add_sub.ys new file mode 100644 index 000000000..d9497b818 --- /dev/null +++ b/tests/arch/machxo2/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys new file mode 100644 index 000000000..83a79a9d6 --- /dev/null +++ b/tests/arch/machxo2/dffs.ys @@ -0,0 +1,19 @@ +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:FACADE_FF +select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 2 t:FACADE_FF t:LUT4 +select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/fsm.ys b/tests/arch/machxo2/fsm.ys new file mode 100644 index 000000000..847a61161 --- /dev/null +++ b/tests/arch/machxo2/fsm.ys @@ -0,0 +1,15 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-max 16 t:LUT4 +select -assert-count 6 t:FACADE_FF +select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/logic.ys b/tests/arch/machxo2/logic.ys new file mode 100644 index 000000000..bf93ab128 --- /dev/null +++ b/tests/arch/machxo2/logic.ys @@ -0,0 +1,8 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 9 t:LUT4 +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys new file mode 100644 index 000000000..6c8aa857c --- /dev/null +++ b/tests/arch/machxo2/mux.ys @@ -0,0 +1,40 @@ +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 2 t:LUT4 + +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 5 t:LUT4 + +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 11 t:LUT4 + +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/run-test.sh b/tests/arch/machxo2/run-test.sh new file mode 100644 index 000000000..4be4b70ae --- /dev/null +++ b/tests/arch/machxo2/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../../gen-tests-makefile.sh +run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" diff --git a/tests/arch/machxo2/shifter.ys b/tests/arch/machxo2/shifter.ys new file mode 100644 index 000000000..87fdab0fa --- /dev/null +++ b/tests/arch/machxo2/shifter.ys @@ -0,0 +1,10 @@ +read_verilog ../common/shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:FACADE_FF +select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys new file mode 100644 index 000000000..9c00a8bcf --- /dev/null +++ b/tests/arch/machxo2/tribuf.ys @@ -0,0 +1,10 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +flatten +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 3 t:FACADE_IO +select -assert-count 1 t:$not +select -assert-none t:FACADE_IO t:$not %% t:* %D diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 1b2788448..c2a23de6d 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -40,10 +40,11 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module +select -assert-max 2 t:LUT3 select -assert-max 2 t:LUT4 select -assert-min 4 t:LUT6 select -assert-max 7 t:LUT6 select -assert-max 2 t:MUXF7 dump -select -assert-none t:LUT6 t:LUT4 t:MUXF7 %% t:* %D +select -assert-none t:LUT6 t:LUT4 t:LUT3 t:MUXF7 %% t:* %D diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys index 2c729832e..c09699411 100644 --- a/tests/arch/xilinx/xilinx_dffopt.ys +++ b/tests/arch/xilinx/xilinx_dffopt.ys @@ -223,3 +223,49 @@ select -assert-count 1 t:LUT2 select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D design -reset + + +read_verilog << EOT + +// FDSE_1, mergeable CE and S, but CE only not worth it. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); + +FDSE_1 ff (.D(tmp[0]), .CE(i[7]), .S(tmp[1]), .Q(o[0])); + +endmodule + +EOT + +read_verilog -lib +/xilinx/cells_sim.v +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +cd t0 +select -assert-count 1 t:FDSE_1 +select -assert-count 1 t:LUT5 +select -assert-none t:FDSE_1 t:LUT5 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +cd t0 +select -assert-count 1 t:FDSE_1 +select -assert-count 2 t:LUT2 +select -assert-none t:FDSE_1 t:LUT2 %% t:* %D + +design -reset diff --git a/tests/opt/opt_share_bug2538.ys b/tests/opt/opt_share_bug2538.ys new file mode 100644 index 000000000..7261c6695 --- /dev/null +++ b/tests/opt/opt_share_bug2538.ys @@ -0,0 +1,20 @@ +read_verilog <<EOT + +module top(...); + +input [3:0] A; +input S; +output [1:0] Y; + +wire [3:0] A1 = A + 1; +wire [3:0] A2 = A + 2; +assign Y = S ? A1[3:2] : A2[3:2]; + +endmodule + +EOT + +proc +alumacc +equiv_opt -assert opt_share + diff --git a/tests/sat/bug2595.ys b/tests/sat/bug2595.ys new file mode 100644 index 000000000..f668fd747 --- /dev/null +++ b/tests/sat/bug2595.ys @@ -0,0 +1,18 @@ +read_ilang <<EOT +module \top + wire input 3 \A + wire width 2 input 2 \B + wire width 2 input 1 \S + wire \Y + cell $pmux \my_pmux + parameter signed \S_WIDTH 2 + parameter signed \WIDTH 1 + connect \A \A + connect \B \B + connect \S \S + connect \Y \Y + end +end +EOT + +assertpmux diff --git a/tests/simple/const_branch_finish.v b/tests/simple/const_branch_finish.v index 8166688e6..f585be87a 100644 --- a/tests/simple/const_branch_finish.v +++ b/tests/simple/const_branch_finish.v @@ -21,9 +21,6 @@ module top; end end generate - begin : unconditional_block - initial `CONSTANT_CHECK - end if (WIDTH == 32) begin : conditional_block initial `CONSTANT_CHECK end diff --git a/tests/simple/const_fold_func.v b/tests/simple/const_fold_func.v new file mode 100644 index 000000000..ee2f12e06 --- /dev/null +++ b/tests/simple/const_fold_func.v @@ -0,0 +1,61 @@ +module top( + input wire [3:0] inp, + output wire [3:0] out1, out2, out3, out4, out5, + output reg [3:0] out6 +); + function automatic [3:0] flip; + input [3:0] inp; + flip = ~inp; + endfunction + + function automatic [3:0] help; + input [3:0] inp; + help = flip(inp); + endfunction + + // while loops are const-eval-only + function automatic [3:0] loop; + input [3:0] inp; + reg [3:0] val; + begin + val = inp; + loop = 1; + while (val != inp) begin + loop = loop * 2; + val = val + 1; + end + end + endfunction + + // not const-eval-only, despite calling a const-eval-only function + function automatic [3:0] help_mul; + input [3:0] inp; + help_mul = inp * loop(2); + endfunction + + // can be elaborated so long as exp is a constant + function automatic [3:0] pow_flip_a; + input [3:0] base, exp; + begin + pow_flip_a = 1; + if (exp > 0) + pow_flip_a = base * pow_flip_a(flip(base), exp - 1); + end + endfunction + + function automatic [3:0] pow_flip_b; + input [3:0] base, exp; + begin + out6[exp] = base & 1; + pow_flip_b = 1; + if (exp > 0) + pow_flip_b = base * pow_flip_b(flip(base), exp - 1); + end + endfunction + + assign out1 = flip(flip(inp)); + assign out2 = help(flip(inp)); + assign out3 = help_mul(inp); + assign out4 = pow_flip_a(flip(inp), 3); + assign out5 = pow_flip_b(2, 2); +endmodule diff --git a/tests/simple/const_func_shadow.v b/tests/simple/const_func_shadow.v new file mode 100644 index 000000000..ca63606d9 --- /dev/null +++ b/tests/simple/const_func_shadow.v @@ -0,0 +1,33 @@ +module top(w, x, y, z); + function [11:0] func; + input reg [2:0] x; + input reg [2:0] y; + begin + x = x * (y + 1); + begin : foo + reg [2:0] y; + y = x + 1; + begin : bar + reg [2:0] x; + x = y + 1; + begin : blah + reg [2:0] y; + y = x + 1; + func[2:0] = y; + end + func[5:3] = x; + end + func[8:6] = y; + end + func[11:9] = x; + end + endfunction + output wire [func(2, 3) - 1:0] w; + output wire [func(1, 3) - 1:0] x; + output wire [func(3, 1) - 1:0] y; + output wire [func(5, 2) - 1:0] z; + assign w = 1'sb1; + assign x = 1'sb1; + assign y = 1'sb1; + assign z = 1'sb1; +endmodule diff --git a/tests/simple/func_block.v b/tests/simple/func_block.v new file mode 100644 index 000000000..be759d1a9 --- /dev/null +++ b/tests/simple/func_block.v @@ -0,0 +1,33 @@ +`default_nettype none + +module top(inp, out1, out2, out3); + input wire [31:0] inp; + + function automatic [31:0] func1; + input [31:0] inp; + reg [31:0] idx; + for (idx = 0; idx < 32; idx = idx + 1) begin : blk + func1[idx] = (idx & 1'b1) ^ inp[idx]; + end + endfunction + + function automatic [31:0] func2; + input [31:0] inp; + reg [31:0] idx; + for (idx = 0; idx < 32; idx = idx + 1) begin : blk + func2[idx] = (idx & 1'b1) ^ inp[idx]; + end + endfunction + + function automatic [31:0] func3; + localparam A = 32 - 1; + parameter B = 1 - 0; + input [31:0] inp; + func3[A:B] = inp[A:B]; + endfunction + + output wire [31:0] out1, out2, out3; + assign out1 = func1(inp); + assign out2 = func2(inp); + assign out3 = func3(inp); +endmodule diff --git a/tests/simple/func_recurse.v b/tests/simple/func_recurse.v new file mode 100644 index 000000000..d61c8cc06 --- /dev/null +++ b/tests/simple/func_recurse.v @@ -0,0 +1,25 @@ +module top( + input wire [3:0] inp, + output wire [3:0] out1, out2 +); + function automatic [3:0] pow_a; + input [3:0] base, exp; + begin + pow_a = 1; + if (exp > 0) + pow_a = base * pow_a(base, exp - 1); + end + endfunction + + function automatic [3:0] pow_b; + input [3:0] base, exp; + begin + pow_b = 1; + if (exp > 0) + pow_b = base * pow_b(base, exp - 1); + end + endfunction + + assign out1 = pow_a(inp, 3); + assign out2 = pow_b(2, 2); +endmodule diff --git a/tests/simple/func_width_scope.v b/tests/simple/func_width_scope.v new file mode 100644 index 000000000..ce81e894e --- /dev/null +++ b/tests/simple/func_width_scope.v @@ -0,0 +1,41 @@ +module top(inp, out1, out2); + input wire signed inp; + + localparam WIDTH_A = 5; + function automatic [WIDTH_A-1:0] func1; + input reg [WIDTH_A-1:0] inp; + func1 = ~inp; + endfunction + wire [func1(0)-1:0] xc; + assign xc = 1'sb1; + wire [WIDTH_A-1:0] xn; + assign xn = func1(inp); + + generate + if (1) begin : blk + localparam WIDTH_A = 6; + function automatic [WIDTH_A-1:0] func2; + input reg [WIDTH_A-1:0] inp; + func2 = ~inp; + endfunction + wire [func2(0)-1:0] yc; + assign yc = 1'sb1; + wire [WIDTH_A-1:0] yn; + assign yn = func2(inp); + + localparam WIDTH_B = 7; + function automatic [WIDTH_B-1:0] func3; + input reg [WIDTH_B-1:0] inp; + func3 = ~inp; + endfunction + wire [func3(0)-1:0] zc; + assign zc = 1'sb1; + wire [WIDTH_B-1:0] zn; + assign zn = func3(inp); + end + endgenerate + + output wire [1023:0] out1, out2; + assign out1 = {xc, 1'b0, blk.yc, 1'b0, blk.zc}; + assign out2 = {xn, 1'b0, blk.yn, 1'b0, blk.zn}; +endmodule diff --git a/tests/simple/genblk_collide.v b/tests/simple/genblk_collide.v new file mode 100644 index 000000000..f42dd2cfc --- /dev/null +++ b/tests/simple/genblk_collide.v @@ -0,0 +1,27 @@ +`default_nettype none + +module top1; + generate + if (1) begin : foo + if (1) begin : bar + wire x; + end + assign bar.x = 1; + wire y; + end + endgenerate +endmodule + +module top2; + genvar i; + generate + if (1) begin : foo + wire x; + for (i = 0; i < 1; i = i + 1) begin : foo + if (1) begin : foo + assign x = 1; + end + end + end + endgenerate +endmodule diff --git a/tests/simple/genblk_dive.v b/tests/simple/genblk_dive.v new file mode 100644 index 000000000..98d0e1f4b --- /dev/null +++ b/tests/simple/genblk_dive.v @@ -0,0 +1,21 @@ +`default_nettype none +module top(output wire x); + generate + if (1) begin : Z + if (1) begin : A + wire x; + if (1) begin : B + wire x; + if (1) begin : C + wire x; + assign B.x = 0; + wire z = A.B.C.x; + end + assign A.x = A.B.C.x; + end + assign B.C.x = B.x; + end + end + endgenerate + assign x = Z.A.x; +endmodule diff --git a/tests/simple/genblk_order.v b/tests/simple/genblk_order.v new file mode 100644 index 000000000..7c3a7a756 --- /dev/null +++ b/tests/simple/genblk_order.v @@ -0,0 +1,18 @@ +`default_nettype none +module top( + output wire out1, + output wire out2 +); + generate + if (1) begin : outer + if (1) begin : foo + wire x = 0; + if (1) begin : foo + wire x = 1; + assign out1 = foo.x; + end + assign out2 = foo.x; + end + end + endgenerate +endmodule diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v new file mode 100644 index 000000000..a04631a20 --- /dev/null +++ b/tests/simple/genblk_port_shadow.v @@ -0,0 +1,10 @@ +module top(x); + generate + if (1) begin : blk + wire x; + assign x = 0; + end + endgenerate + output wire x; + assign x = blk.x; +endmodule diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 12327b36e..445c88ba8 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -167,7 +167,7 @@ module gen_test7; reg [2:0] out2; wire [2:0] out3; generate - begin : cond + if (1) begin : cond reg [2:0] sub_out1; reg [2:0] sub_out2; wire [2:0] sub_out3; @@ -215,9 +215,9 @@ module gen_test8; wire [1:0] x = 2'b11; generate - begin : A + if (1) begin : A wire [1:0] x; - begin : B + if (1) begin : B wire [1:0] x = 2'b00; `ASSERT(x == 0) `ASSERT(A.x == 2) @@ -228,7 +228,7 @@ module gen_test8; `ASSERT(gen_test8.A.C.x == 1) `ASSERT(gen_test8.A.B.x == 0) end - begin : C + if (1) begin : C wire [1:0] x = 2'b01; `ASSERT(x == 1) `ASSERT(A.x == 2) @@ -260,3 +260,66 @@ module gen_test8; `ASSERT(gen_test8.A.C.x == 1) `ASSERT(gen_test8.A.B.x == 0) endmodule + +// ------------------------------------------ + +module gen_test9; + +// `define VERIFY +`ifdef VERIFY + `define ASSERT(expr) assert property (expr); +`else + `define ASSERT(expr) +`endif + + wire [1:0] w = 2'b11; + generate + begin : A + wire [1:0] x; + begin : B + wire [1:0] y = 2'b00; + `ASSERT(w == 3) + `ASSERT(x == 2) + `ASSERT(y == 0) + `ASSERT(A.x == 2) + `ASSERT(A.C.z == 1) + `ASSERT(A.B.y == 0) + `ASSERT(gen_test9.w == 3) + `ASSERT(gen_test9.A.x == 2) + `ASSERT(gen_test9.A.C.z == 1) + `ASSERT(gen_test9.A.B.y == 0) + end + begin : C + wire [1:0] z = 2'b01; + `ASSERT(w == 3) + `ASSERT(x == 2) + `ASSERT(z == 1) + `ASSERT(A.x == 2) + `ASSERT(A.C.z == 1) + `ASSERT(A.B.y == 0) + `ASSERT(gen_test9.w == 3) + `ASSERT(gen_test9.A.x == 2) + `ASSERT(gen_test9.A.C.z == 1) + `ASSERT(gen_test9.A.B.y == 0) + end + assign x = B.y ^ 2'b11 ^ C.z; + `ASSERT(x == 2) + `ASSERT(A.x == 2) + `ASSERT(A.C.z == 1) + `ASSERT(A.B.y == 0) + `ASSERT(gen_test9.w == 3) + `ASSERT(gen_test9.A.x == 2) + `ASSERT(gen_test9.A.C.z == 1) + `ASSERT(gen_test9.A.B.y == 0) + end + endgenerate + + `ASSERT(w == 3) + `ASSERT(A.x == 2) + `ASSERT(A.C.z == 1) + `ASSERT(A.B.y == 0) + `ASSERT(gen_test9.w == 3) + `ASSERT(gen_test9.A.x == 2) + `ASSERT(gen_test9.A.C.z == 1) + `ASSERT(gen_test9.A.B.y == 0) +endmodule diff --git a/tests/simple/local_loop_var.sv b/tests/simple/local_loop_var.sv new file mode 100644 index 000000000..46b4e5c22 --- /dev/null +++ b/tests/simple/local_loop_var.sv @@ -0,0 +1,11 @@ +module top(out); + output integer out; + initial begin + integer i; + for (i = 0; i < 5; i = i + 1) + if (i == 0) + out = 1; + else + out += 2 ** i; + end +endmodule diff --git a/tests/simple/loop_var_shadow.v b/tests/simple/loop_var_shadow.v new file mode 100644 index 000000000..0222a4493 --- /dev/null +++ b/tests/simple/loop_var_shadow.v @@ -0,0 +1,15 @@ +module top(out); + genvar i; + generate + for (i = 0; i < 2; i = i + 1) begin : loop + localparam j = i + 1; + if (1) begin : blk + localparam i = j + 1; + wire [i:0] x; + assign x = 1'sb1; + end + end + endgenerate + output wire [63:0] out; + assign out = {loop[0].blk.x, loop[1].blk.x}; +endmodule diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv new file mode 100644 index 000000000..75c4cd136 --- /dev/null +++ b/tests/simple/macro_arg_spaces.sv @@ -0,0 +1,28 @@ +module top( + input wire [31:0] i, + output wire [31:0] x, y, z +); + +`define BAR(a) a +`define FOO(a = function automatic [31:0] f) a + +`BAR(function automatic [31:0] a); + input [31:0] i; + a = i * 2; +endfunction + +`FOO(); + input [31:0] i; + f = i * 3; +endfunction + +`FOO(function automatic [31:0] b); + input [31:0] i; + b = i * 5; +endfunction + +assign x = a(i); +assign y = f(i); +assign z = b(i); + +endmodule diff --git a/tests/simple/macro_arg_surrounding_spaces.v b/tests/simple/macro_arg_surrounding_spaces.v new file mode 100644 index 000000000..3dbb5ea01 --- /dev/null +++ b/tests/simple/macro_arg_surrounding_spaces.v @@ -0,0 +1,20 @@ +module top( + IDENT_V_, + IDENT_W_, + IDENT_X_, + IDENT_Y_, + IDENT_Z_, + IDENT_A_, + IDENT_B_, + IDENT_C_ +); + `define MACRO(dummy, x) IDENT_``x``_ + output wire IDENT_V_; + output wire `MACRO(_,W); + output wire `MACRO(_, X); + output wire `MACRO(_,Y ); + output wire `MACRO(_, Z ); + output wire `MACRO(_, A); + output wire `MACRO(_,B ); + output wire `MACRO(_, C ); +endmodule diff --git a/tests/simple/named_genblk.v b/tests/simple/named_genblk.v new file mode 100644 index 000000000..b8300fc4d --- /dev/null +++ b/tests/simple/named_genblk.v @@ -0,0 +1,27 @@ +`default_nettype none +module top; + generate + if (1) begin + wire t; + begin : foo + wire x; + end + wire u; + end + begin : bar + wire x; + wire y; + begin : baz + wire x; + wire z; + end + end + endgenerate + assign genblk1.t = 1; + assign genblk1.foo.x = 1; + assign genblk1.u = 1; + assign bar.x = 1; + assign bar.y = 1; + assign bar.baz.x = 1; + assign bar.baz.z = 1; +endmodule diff --git a/tests/simple/nested_genblk_resolve.v b/tests/simple/nested_genblk_resolve.v new file mode 100644 index 000000000..da5593f8a --- /dev/null +++ b/tests/simple/nested_genblk_resolve.v @@ -0,0 +1,14 @@ +`default_nettype none +module top; + generate + if (1) begin + wire x; + genvar i; + for (i = 0; i < 1; i = i + 1) begin + if (1) begin + assign x = 1; + end + end + end + endgenerate +endmodule diff --git a/tests/simple/unnamed_block_decl.sv b/tests/simple/unnamed_block_decl.sv new file mode 100644 index 000000000..e81b457a8 --- /dev/null +++ b/tests/simple/unnamed_block_decl.sv @@ -0,0 +1,17 @@ +module top(z); + output integer z; + initial begin + integer x; + x = 1; + begin + integer y; + y = x + 1; + begin + integer z; + z = y + 1; + y = z + 1; + end + z = y + 1; + end + end +endmodule diff --git a/tests/svtypes/typedef_struct_port.sv b/tests/svtypes/typedef_struct_port.sv new file mode 100644 index 000000000..ecc03bee8 --- /dev/null +++ b/tests/svtypes/typedef_struct_port.sv @@ -0,0 +1,111 @@ +package p; + +typedef struct packed { + byte a; + byte b; +} p_t; + +typedef logic [31:0] l_t; + +endpackage + +module foo1( + input p::p_t p, + output p::p_t o +); + assign o = p; +endmodule + +module foo2(p, o); + input p::p_t p; + output p::p_t o; + assign o = p; +endmodule + +module foo3(input p::l_t p, input p::l_t o); + assign o = p; +endmodule + +module foo4(input logic [15:0] p, input logic [15:0] o); + assign o = p; +endmodule + +module test_parser(a,b,c,d,e,f,g,h,i); +input [7:0] a; // no explicit net declaration - net is unsigned +input [7:0] b; +input signed [7:0] c; +input signed [7:0] d; // no explicit net declaration - net is signed +output [7:0] e; // no explicit net declaration - net is unsigned +output [7:0] f; +output signed [7:0] g; +output signed [7:0] h; // no explicit net declaration - net is signed +output unsigned [7:0] i; +wire signed [7:0] b; // port b inherits signed attribute from net decl. +wire [7:0] c; // net c inherits signed attribute from port +logic signed [7:0] f;// port f inherits signed attribute from logic decl. +logic [7:0] g; // logic g inherits signed attribute from port + + assign a = 8'b10001111; + assign b = 8'b10001111; + assign c = 8'b10001111; + assign d = 8'b10001111; + assign e = 8'b10001111; + assign f = 8'b10001111; + assign g = 8'b10001111; + assign h = 8'b10001111; + assign i = 8'b10001111; + always_comb begin + assert($unsigned(143) == a); + assert($signed(-113) == b); + assert($signed(-113) == c); + assert($signed(-113) == d); + assert($unsigned(143) == e); + assert($unsigned(143) == f); + assert($signed(-113) == g); + assert($signed(-113) == h); + assert($unsigned(143) == i); + end +endmodule + +module top; + p::p_t ps; + assign ps.a = 8'hAA; + assign ps.b = 8'h55; + foo1 foo(.p(ps)); + + p::p_t body; + assign body.a = 8'hBB; + assign body.b = 8'h66; + foo2 foo_b(.p(body)); + + typedef p::l_t local_alias; + + local_alias l_s; + assign l_s = 32'hAAAAAAAA; + foo3 foo_l(.p(l_s)); + + typedef logic [15:0] sl_t; + + sl_t sl_s; + assign sl_s = 16'hBBBB; + foo4 foo_sl(.p(sl_s)); + + typedef sl_t local_alias_st; + + local_alias_st lsl_s; + assign lsl_s = 16'hCCCC; + foo4 foo_lsl(.p(lsl_s)); + + const logic j = 1'b1; + + always_comb begin + assert(8'hAA == ps.a); + assert(8'h55 == ps.b); + assert(8'hBB == body.a); + assert(8'h66 == body.b); + assert(32'hAAAAAAAA == l_s); + assert(16'hBBBB == sl_s); + assert(16'hCCCC == lsl_s); + assert(1'b1 == j); + end +endmodule diff --git a/tests/svtypes/typedef_struct_port.ys b/tests/svtypes/typedef_struct_port.ys new file mode 100644 index 000000000..5b75c3105 --- /dev/null +++ b/tests/svtypes/typedef_struct_port.ys @@ -0,0 +1,6 @@ +read_verilog -sv typedef_struct_port.sv +hierarchy; proc; opt +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all +select -module test_parser +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/techmap/adff2dff.ys b/tests/techmap/adff2dff.ys new file mode 100644 index 000000000..53f7d2f08 --- /dev/null +++ b/tests/techmap/adff2dff.ys @@ -0,0 +1,19 @@ +read_verilog -icells << EOT +module top(...); + +input [1:0] D; +input C, R; +output [1:0] Q; + +always @(posedge C, posedge R) + if (R) + Q <= 0; + else + Q <= D; + +endmodule +EOT + +proc + +equiv_opt -async2sync techmap -map +/adff2dff.v diff --git a/tests/techmap/dff2ff.ys b/tests/techmap/dff2ff.ys new file mode 100644 index 000000000..5adf14b07 --- /dev/null +++ b/tests/techmap/dff2ff.ys @@ -0,0 +1,16 @@ +read_verilog -icells << EOT +module top(...); + +input [1:0] D; +input C; +output [1:0] Q; + +always @(posedge C) + Q <= D; + +endmodule +EOT + +proc + +equiv_opt techmap -map +/dff2ff.v diff --git a/tests/techmap/pmux2mux.ys b/tests/techmap/pmux2mux.ys new file mode 100644 index 000000000..1714a6b87 --- /dev/null +++ b/tests/techmap/pmux2mux.ys @@ -0,0 +1,15 @@ +read_verilog -icells << EOT +module top(...); + +input [3:0] A; +input [3:0] B0; +input [3:0] B1; +input [1:0] S; +output [3:0] O; + +\$pmux #(.WIDTH(4), .S_WIDTH(2)) pm (.A(A), .B({B1, B0}), .S(S), .Y(O)); + +endmodule +EOT + +equiv_opt techmap -map +/pmux2mux.v diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 12d4e5048..2bb6c7179 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -4,3 +4,4 @@ /write_gzip.v.gz /run-test.mk /plugin.so +/plugin.so.dSYM diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.sv index 358fb439a..f28d06e68 100644 --- a/tests/various/const_arg_loop.v +++ b/tests/various/const_arg_loop.sv @@ -20,11 +20,11 @@ module top; endfunction function automatic [31:0] operation2; - input [4:0] var; + input [4:0] inp; input integer num; begin - var[0] = var[0] ^ 1; - operation2 = num * var; + inp[0] = inp[0] ^ 1; + operation2 = num * inp; end endfunction @@ -79,15 +79,14 @@ module top; wire [31:0] x5; assign x5 = operation5(64); -// `define VERIFY -`ifdef VERIFY - assert property (a == 2); - assert property (A == 3); - assert property (x1 == 16); - assert property (x1b == 16); - assert property (x2 == 4); - assert property (x3 == 16); - assert property (x4 == a << 1); - assert property (x5 == 64); -`endif + always_comb begin + assert(a == 2); + assert(A == 3); + assert(x1 == 16); + assert(x1b == 16); + assert(x2 == 4); + assert(x3 == 16); + assert(x4 == a << 1); + assert(x5 == 64); + end endmodule diff --git a/tests/various/const_arg_loop.ys b/tests/various/const_arg_loop.ys index b039bda10..392532213 100644 --- a/tests/various/const_arg_loop.ys +++ b/tests/various/const_arg_loop.ys @@ -1 +1,6 @@ -read_verilog const_arg_loop.v +read_verilog -sv const_arg_loop.sv +hierarchy +proc +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/various/const_func.v b/tests/various/const_func.sv index 541e63b19..af65f5c73 100644 --- a/tests/various/const_func.v +++ b/tests/various/const_func.sv @@ -62,26 +62,25 @@ module top(out); localparam signed Y = $floor(W / X); localparam signed Z = negate($floor(W / X)); -// `define VERIFY -`ifdef VERIFY - assert property (a1 == 0); - assert property (a2 == 0); - assert property (a3 == "BAR"); - assert property (a4 == 0); - assert property (b1 == "FOO"); - assert property (b2 == "FOO"); - assert property (b3 == 0); - assert property (b4 == "HI"); - assert property (c1 == 1); - assert property (c2 == 1); - assert property (c3 == 0); - assert property (c4 == 0); - assert property (d1 == 0); - assert property (d2 == 0); - assert property (d3 == 1); - assert property (d4 == 1); + always_comb begin + assert(a1 == 0); + assert(a2 == 0); + assert(a3 == "BAR"); + assert(a4 == 0); + assert(b1 == "FOO"); + assert(b2 == "FOO"); + assert(b3 == 0); + assert(b4 == "HI"); + assert(c1 == 1); + assert(c2 == 1); + assert(c3 == 0); + assert(c4 == 0); + assert(d1 == 0); + assert(d2 == 0); + assert(d3 == 1); + assert(d4 == 1); - assert property (Y == 3); - assert property (Z == ~3); -`endif + assert(Y == 3); + assert(Z == ~3); + end endmodule diff --git a/tests/various/const_func.ys b/tests/various/const_func.ys index 5e3c04105..2f60acfe6 100644 --- a/tests/various/const_func.ys +++ b/tests/various/const_func.ys @@ -1 +1,7 @@ -read_verilog const_func.v +read_verilog -sv const_func.sv +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/various/countbits.sv b/tests/various/countbits.sv new file mode 100644 index 000000000..5762217bb --- /dev/null +++ b/tests/various/countbits.sv @@ -0,0 +1,69 @@ +module top; + + assert property ($countbits(15'b011xxxxzzzzzzzz, '0 ) == 1); + assert property ($countbits(15'b011xxxxzzzzzzzz, '1 ) == 2); + assert property ($countbits(15'b011xxxxzzzzzzzz, 'x ) == 4); + assert property ($countbits(15'b011xxxxzzzzzzzz, 'z ) == 8); + assert property ($countbits(15'b011xxxxzzzzzzzz, '0, '1 ) == 3); + assert property ($countbits(15'b011xxxxzzzzzzzz, '1, '1, '0 ) == 3); + assert property ($countbits(15'b011xxxxzzzzzzzz, '0, 'x ) == 5); + assert property ($countbits(15'b011xxxxzzzzzzzz, '0, 'z ) == 9); + assert property ($countbits(15'bz1x10xzxzzxzzzz, '0, 'z ) == 9); + assert property ($countbits(15'b011xxxxzzzzzzzz, 'x, 'z ) == 12); + assert property ($countbits(15'b011xxxxzzzzzzzz, '1, 'z ) == 10); + assert property ($countbits(15'b011xxxxzzzzzzzz, '1, 'x, 'z ) == 14); + assert property ($countbits(15'b011xxxxzzzzzzzz, '1, 'x, 'z, '0) == 15); + + assert property ($countbits(0, '0) == 32); // test integers + assert property ($countbits(0, '1) == 0); + assert property ($countbits(80'b0, '0) == 80); // test something bigger than integer + assert property ($countbits(80'bx0, 'x) == 79); + + always_comb begin + logic one; + logic [1:0] two; + logic [3:0] four; + + // Make sure that the width of the whole expression doesn't affect the width of the shift + // operations inside the function. + one = $countbits(3'b100, '1) & 1'b1; + two = $countbits(3'b111, '1) & 2'b11; + four = $countbits(3'b111, '1) & 4'b1111; + + assert (one == 1); + assert (two == 3); + assert (four == 3); + end + + assert property ($countones(8'h00) == 0); + assert property ($countones(8'hff) == 8); + assert property ($countones(8'ha5) == 4); + assert property ($countones(8'h13) == 3); + + logic test1 = 1'b1; + logic [4:0] test5 = 5'b10101; + + assert property ($countones(test1) == 1); + assert property ($countones(test5) == 3); + + assert property ($isunknown(8'h00) == 0); + assert property ($isunknown(8'hff) == 0); + assert property ($isunknown(8'hx0) == 1); + assert property ($isunknown(8'h1z) == 1); + assert property ($isunknown(8'hxz) == 1); + + assert property ($onehot(8'h00) == 0); + assert property ($onehot(8'hff) == 0); + assert property ($onehot(8'h01) == 1); + assert property ($onehot(8'h80) == 1); + assert property ($onehot(8'h81) == 0); + assert property ($onehot(8'h20) == 1); + + assert property ($onehot0(8'h00) == 1); + assert property ($onehot0(8'hff) == 0); + assert property ($onehot0(8'h01) == 1); + assert property ($onehot0(8'h80) == 1); + assert property ($onehot0(8'h81) == 0); + assert property ($onehot0(8'h20) == 1); + +endmodule diff --git a/tests/various/countbits.ys b/tests/various/countbits.ys new file mode 100644 index 000000000..a556f7c5d --- /dev/null +++ b/tests/various/countbits.ys @@ -0,0 +1,7 @@ +read_verilog -sv countbits.sv +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/various/fib_tern.v b/tests/various/fib_tern.v new file mode 100644 index 000000000..fefde74ce --- /dev/null +++ b/tests/various/fib_tern.v @@ -0,0 +1,70 @@ +module gate( + off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9 +); + input wire signed [31:0] off; + + function automatic blah( + input x + ); + blah = x; + endfunction + + function automatic integer fib( + input integer k + ); + fib = k == 0 + ? 0 + : k == 1 + ? 1 + : fib(k - 1) + fib(k - 2); + endfunction + + function automatic integer fib_wrap( + input integer k, + output integer o + ); + o = off + fib(k); + endfunction + + output integer fib0; + output integer fib1; + output integer fib2; + output integer fib3; + output integer fib4; + output integer fib5; + output integer fib6; + output integer fib7; + output integer fib8; + output integer fib9; + + initial begin : blk + integer unused; + unused = fib_wrap(0, fib0); + unused = fib_wrap(1, fib1); + unused = fib_wrap(2, fib2); + unused = fib_wrap(3, fib3); + unused = fib_wrap(4, fib4); + unused = fib_wrap(5, fib5); + unused = fib_wrap(6, fib6); + unused = fib_wrap(7, fib7); + unused = fib_wrap(8, fib8); + unused = fib_wrap(9, fib9); + end +endmodule + +module gold( + off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9 +); + input wire signed [31:0] off; + + output integer fib0 = off + 0; + output integer fib1 = off + 1; + output integer fib2 = off + 1; + output integer fib3 = off + 2; + output integer fib4 = off + 3; + output integer fib5 = off + 5; + output integer fib6 = off + 8; + output integer fib7 = off + 13; + output integer fib8 = off + 21; + output integer fib9 = off + 34; +endmodule diff --git a/tests/various/fib_tern.ys b/tests/various/fib_tern.ys new file mode 100644 index 000000000..e5bf186e1 --- /dev/null +++ b/tests/various/fib_tern.ys @@ -0,0 +1,6 @@ +read_verilog fib_tern.v +hierarchy +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/various/gen_if_null.v b/tests/various/gen_if_null.v index a12ac6288..992bc68b3 100644 --- a/tests/various/gen_if_null.v +++ b/tests/various/gen_if_null.v @@ -1,13 +1,17 @@ -module test(x, y, z); +`default_nettype none +module test; localparam OFF = 0; generate if (OFF) ; - else input x; - if (!OFF) input y; + else wire x; + if (!OFF) wire y; else ; if (OFF) ; else ; if (OFF) ; - input z; + wire z; endgenerate + assign genblk1.x = 0; + assign genblk2.y = 0; + assign z = 0; endmodule diff --git a/tests/various/gen_if_null.ys b/tests/various/gen_if_null.ys index 31dfc444b..0733e3a94 100644 --- a/tests/various/gen_if_null.ys +++ b/tests/various/gen_if_null.ys @@ -1,4 +1,4 @@ read_verilog gen_if_null.v -select -assert-count 1 test/x -select -assert-count 1 test/y +select -assert-count 1 test/genblk1.x +select -assert-count 1 test/genblk2.y select -assert-count 1 test/z diff --git a/tests/various/port_sign_extend.v b/tests/various/port_sign_extend.v index 446268268..813ceb503 100644 --- a/tests/various/port_sign_extend.v +++ b/tests/various/port_sign_extend.v @@ -24,8 +24,8 @@ module PassThrough(a, b); assign b = a; endmodule -module act(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2); - output wire [3:0] o1, o2, o3, o4, o5, o6; +module act(o1, o2, o3, o4, o5, o6, o7, o8, o9, yay1, nay1, yay2, nay2); + output wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8, o9; // unsigned constant PassThrough pt1(1'b1, o1); @@ -52,6 +52,17 @@ module act(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2); wire signed [2:0] tmp6b = 3'b001; PassThrough pt6(tmp6a ? tmp6a : tmp6b, o6); + wire signed [2:0] tmp7 = 3'b011; + PassThrough pt7(~tmp7, o7); + + reg signed [2:0] tmp8 [0:0]; + initial tmp8[0] = 3'b101; + PassThrough pt8(tmp8[0], o8); + + wire signed [2:0] tmp9a = 3'b100; + wire signed [1:0] tmp9b = 2'b11; + PassThrough pt9(0 ? tmp9a : tmp9b, o9); + output wire [2:0] yay1, nay1; GeneratorSigned1 os1(yay1); GeneratorUnsigned1 ou1(nay1); @@ -61,8 +72,8 @@ module act(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2); GeneratorUnsigned2 ou2(nay2); endmodule -module ref(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2); - output wire [3:0] o1, o2, o3, o4, o5, o6; +module ref(o1, o2, o3, o4, o5, o6, o7, o8, o9, yay1, nay1, yay2, nay2); + output wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8, o9; assign o1 = 4'b0001; assign o2 = 4'b0001; @@ -70,6 +81,9 @@ module ref(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2); assign o4 = 4'b1111; assign o5 = 4'b1110; assign o6 = 4'b1100; + assign o7 = 4'b1100; + assign o8 = 4'b1101; + assign o9 = 4'b1111; output wire [2:0] yay1, nay1; assign yay1 = 3'b111; diff --git a/tests/various/port_sign_extend.ys b/tests/various/port_sign_extend.ys index 0a6a93810..6d1adf7f3 100644 --- a/tests/various/port_sign_extend.ys +++ b/tests/various/port_sign_extend.ys @@ -1,22 +1,29 @@ -read_verilog port_sign_extend.v +read_verilog -nomem2reg port_sign_extend.v hierarchy flatten +proc +memory equiv_make ref act equiv equiv_simple equiv_status -assert delete -read_verilog port_sign_extend.v +read_verilog -nomem2reg port_sign_extend.v flatten +proc +memory equiv_make ref act equiv equiv_simple equiv_status -assert delete -read_verilog port_sign_extend.v +read_verilog -nomem2reg port_sign_extend.v hierarchy +proc +memory equiv_make ref act equiv prep -flatten -top equiv +equiv_induct equiv_status -assert diff --git a/tests/various/rand_const.sv b/tests/various/rand_const.sv new file mode 100644 index 000000000..be00812c0 --- /dev/null +++ b/tests/various/rand_const.sv @@ -0,0 +1,8 @@ +module top; + rand const reg rx; + const reg ry; + rand reg rz; + rand const integer ix; + const integer iy; + rand integer iz; +endmodule diff --git a/tests/various/rand_const.ys b/tests/various/rand_const.ys new file mode 100644 index 000000000..74e43c7cc --- /dev/null +++ b/tests/various/rand_const.ys @@ -0,0 +1 @@ +read_verilog -sv rand_const.sv diff --git a/tests/verilog/atom_type_signedness.ys b/tests/verilog/atom_type_signedness.ys new file mode 100644 index 000000000..22bbe6efc --- /dev/null +++ b/tests/verilog/atom_type_signedness.ys @@ -0,0 +1,19 @@ +read_verilog -dump_ast1 -dump_ast2 -sv <<EOT +module dut(); + +enum integer { uInteger = -10 } a; +enum int { uInt = -11 } b; +enum shortint { uShortInt = -12 } c; +enum byte { uByte = -13 } d; + +always_comb begin + assert(-10 == uInteger); + assert(-11 == uInt); + assert(-12 == uShortInt); + assert(-13 == uByte); +end +endmodule +EOT +hierarchy; proc; opt +select -module dut +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/block_labels.ys b/tests/verilog/block_labels.ys new file mode 100644 index 000000000..e76bcf771 --- /dev/null +++ b/tests/verilog/block_labels.ys @@ -0,0 +1,26 @@ +read_verilog <<EOT +module foo; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end : a +endmodule +EOT +read_verilog <<EOT +module foo2; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end +endmodule +EOT + +logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1 +read_verilog <<EOT +module foo3; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end : b +endmodule +EOT diff --git a/tests/verilog/bug2493.ys b/tests/verilog/bug2493.ys new file mode 100644 index 000000000..380d2a823 --- /dev/null +++ b/tests/verilog/bug2493.ys @@ -0,0 +1,12 @@ +logger -expect error "Failed to detect width for identifier \\genblk1\.y!" 1 +read_verilog <<EOT +module top1; + wire x; + generate + if (1) begin + mod y(); + assign x = y; + end + endgenerate +endmodule +EOT diff --git a/tests/verilog/bug656.v b/tests/verilog/bug656.v new file mode 100644 index 000000000..068d045fd --- /dev/null +++ b/tests/verilog/bug656.v @@ -0,0 +1,21 @@ +module top #( + parameter WIDTH = 6 +) ( + input [WIDTH-1:0] a_i, + input [WIDTH-1:0] b_i, + output [WIDTH-1:0] z_o +); + genvar g; + generate + for (g = 0; g < WIDTH; g = g + 1) begin + if (g > 2) begin + wire tmp; + assign tmp = a_i[g] || b_i[g]; + assign z_o[g] = tmp; + end + else begin + assign z_o[g] = a_i[g] && b_i[g]; + end + end + endgenerate +endmodule diff --git a/tests/verilog/bug656.ys b/tests/verilog/bug656.ys new file mode 100644 index 000000000..7f367341a --- /dev/null +++ b/tests/verilog/bug656.ys @@ -0,0 +1,13 @@ +read_verilog bug656.v + +select -assert-count 1 top/a_i +select -assert-count 1 top/b_i +select -assert-count 1 top/z_o + +select -assert-none top/genblk1[0].genblk1.tmp +select -assert-none top/genblk1[1].genblk1.tmp +select -assert-none top/genblk1[2].genblk1.tmp + +select -assert-count 1 top/genblk1[3].genblk1.tmp +select -assert-count 1 top/genblk1[4].genblk1.tmp +select -assert-count 1 top/genblk1[5].genblk1.tmp diff --git a/tests/verilog/conflict_assert.ys b/tests/verilog/conflict_assert.ys new file mode 100644 index 000000000..121a0cf51 --- /dev/null +++ b/tests/verilog/conflict_assert.ys @@ -0,0 +1,8 @@ +logger -expect error "Cannot add procedural assertion `\\x' because a signal with the same name was already created" 1 +read_verilog -sv <<EOT +module top; + wire x, y; + always @* + x: assert(y == 1); +endmodule +EOT diff --git a/tests/verilog/conflict_cell_memory.ys b/tests/verilog/conflict_cell_memory.ys new file mode 100644 index 000000000..ddc67596f --- /dev/null +++ b/tests/verilog/conflict_cell_memory.ys @@ -0,0 +1,9 @@ +logger -expect error "Cannot add cell `\\x' because a memory with the same name was already created" 1 +read_verilog <<EOT +module mod; +endmodule +module top; + reg [2:0] x [0:0]; + mod x(); +endmodule +EOT diff --git a/tests/verilog/conflict_interface_port.ys b/tests/verilog/conflict_interface_port.ys new file mode 100644 index 000000000..b97ec029e --- /dev/null +++ b/tests/verilog/conflict_interface_port.ys @@ -0,0 +1,17 @@ +logger -expect error "Cannot add interface port `\\i' because a signal with the same name was already created" 1 +read_verilog -sv <<EOT +interface intf; + logic x; + assign x = 1; + modport m(input x); +endinterface +module mod(intf.m i); + wire x; + assign x = i.x; + wire i; +endmodule +module top; + intf i(); + mod m(i); +endmodule +EOT diff --git a/tests/verilog/conflict_memory_wire.ys b/tests/verilog/conflict_memory_wire.ys new file mode 100644 index 000000000..5c296074f --- /dev/null +++ b/tests/verilog/conflict_memory_wire.ys @@ -0,0 +1,7 @@ +logger -expect error "Cannot add memory `\\x' because a signal with the same name was already created" 1 +read_verilog <<EOT +module top; + reg [2:0] x; + reg [2:0] x [0:0]; +endmodule +EOT diff --git a/tests/verilog/conflict_pwire.ys b/tests/verilog/conflict_pwire.ys new file mode 100644 index 000000000..ecc30d33a --- /dev/null +++ b/tests/verilog/conflict_pwire.ys @@ -0,0 +1,8 @@ +logger -expect error "Cannot add pwire `\\x' because a signal with the same name was already created" 1 +read_verilog -pwires <<EOT +module top; + wire x; + assign x = 1; + localparam x = 2; +endmodule +EOT diff --git a/tests/verilog/conflict_wire_memory.ys b/tests/verilog/conflict_wire_memory.ys new file mode 100644 index 000000000..77520fea9 --- /dev/null +++ b/tests/verilog/conflict_wire_memory.ys @@ -0,0 +1,7 @@ +logger -expect error "Cannot add signal `\\x' because a memory with the same name was already created" 1 +read_verilog <<EOT +module top; + reg [2:0] x [0:0]; + reg [2:0] x; +endmodule +EOT diff --git a/tests/verilog/delay_mintypmax.ys b/tests/verilog/delay_mintypmax.ys new file mode 100644 index 000000000..74359f557 --- /dev/null +++ b/tests/verilog/delay_mintypmax.ys @@ -0,0 +1,213 @@ +logger -expect-no-warnings +read_verilog <<EOT +module test (a, b, c, y); + input a; + input signed [1:0] b; + input signed [2:0] c; + output y; + assign #(12.5 : 14.5 : 20) y = ^(a ? b : c); +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog << EOT +module test (input [7:0] a, b, c, d, output [7:0] x, y, z); + assign #(20:20:25) x = a + b, y = b + c, z = c + d; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog << EOT +module test (input [7:0] a, b, c, d, output [7:0] x, y, z); + assign #(20:20:25, 40:45:50, 60:65:75) x = a + b, y = b + c, z = c + d; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test (a, b, c, y); + localparam TIME_STEP = 0.011; + input signed [3:0] a; + input signed [1:0] b; + input signed [1:0] c; + output [5:0] y; + assign #(TIME_STEP:TIME_STEP:TIME_STEP) y = (a >> b) >>> c; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test; + wire o, a, b; + and #(1:2:3, 4:5:6) and_gate (o, a, b); + wire #(1:2:3, 4:5:6, 7:8:9) x; + assign o = x; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test; + localparam TIME_TYP = 0.7; + wire o, a, b; + and #(0:TIME_TYP:2) and_gate (o, a, b); + wire #(2:TIME_TYP:4) x; + assign o = x; +endmodule +EOT + +design -reset +logger -expect warning "Yosys has only limited support for tri-state logic at the moment." 1 +read_verilog <<EOT +module test (input en, input a, input b, output c); + wire [15:0] add0_res = a + b; + assign #(15:20:30) c = (en) ? a : 1'bz; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test (input en, d, t_min, t, t_max); + reg o; + always @* + if (en) + o = #(t_min : t : t_max, t_min : t : t_max) ~d; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test #(parameter DELAY_RISE = 0, DELAY_FALL = 0, DELAY_Z = 0) + (input clock, input reset, input req_0, input req_1, output gnt_0, output gnt_1); + parameter SIZE = 3; + parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100; + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + reg gnt_0, gnt_1; + + always @ (state or req_0 or req_1) + begin : FSM_COMBO + next_state = 3'b000; + case (state) + IDLE : if (req_0 == 1'b1) begin + next_state = #(DELAY_RISE-1 : DELAY_RISE : DELAY_RISE+1) GNT0; + end else if (req_1 == 1'b1) begin + next_state = #(DELAY_FALL/1.2 : DELAY_FALL : DELAY_FALL*2.5) GNT1; + end else begin + next_state = #(DELAY_Z : DELAY_Z : DELAY_Z) IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + #(DELAY_RISE : DELAY_RISE : DELAY_FALL) next_state = GNT0; + end else begin + #DELAY_RISE next_state = IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + #10 next_state = GNT1; + end else begin + #(10:10:15, 20:25:25) next_state = IDLE; + end + default : next_state = IDLE; + endcase + end + + always @ (posedge clock) + begin : FSM_SEQ + if (reset == 1'b1) begin + #(10:10:15) state <= IDLE; + end else begin + #(10) state <= next_state; + end + end + + always @ (posedge clock) + begin : FSM_OUTPUT + if (reset == 1'b1) begin + gnt_0 <= #(8:9:10) 1'b0; + gnt_1 <= #1 1'b0; + end else begin + case (state) + IDLE : begin + gnt_0 <= #(8:9:10) 1'b0; + gnt_1 <= #1 1'b0; + end + GNT0 : begin + gnt_0 <= #(4:5:6,8:9:10) 1'b1; + gnt_1 <= #1 1'b0; + end + GNT1 : begin + gnt_0 <= #(2:3:4,4:5:6,8:9:10) 1'b0; + gnt_1 <= #1 1'b1; + end + default : begin + gnt_0 <= 1'b0; + gnt_1 <= 1'b0; + end + endcase + end + end +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test; + reg q; + initial begin + q = 1; + #(1:2:2) q = 0; + end +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test #(parameter hyst = 16) + (input [0:1] inA, input rst, output reg out); + parameter real updatePeriod = 100.0; + initial out = 1'b0; + always #(updatePeriod-5:updatePeriod:updatePeriod+5) begin + if (rst) out <= 1'b0; + else if (inA[0] > inA[1]) out <= 1'b1; + else if (inA[0] < inA[1] - hyst) out <= 1'b0; + end +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test; + reg clk; + initial clk = 1'b0; + always #(100:180:230) clk = ~clk; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test; + reg clk; + initial clk = 1'b0; + always clk = #(100:180:230, 100:180:230) ~clk; + task t_test; + sig_036_A <= #(2, 4, 5.5) 0; + sig_036_B <= #(1.3, 3) 0; + sig_036_S <= #(2) 0; + #(100 : 200 : 300, 400 : 500 : 600, 700 : 800 : 900); + sig_036_A <= #(1.5:2.5:3.0, 3:4:5, 7) ~0; + sig_036_B <= #(2, 4:6:6) ~0; + sig_036_S <= #(1.5:2.5:3.0) ~0; + #100; + endtask +endmodule +EOT diff --git a/tests/verilog/delay_risefall.ys b/tests/verilog/delay_risefall.ys new file mode 100644 index 000000000..ffbe1909d --- /dev/null +++ b/tests/verilog/delay_risefall.ys @@ -0,0 +1,225 @@ +logger -expect-no-warnings +read_verilog <<EOT +module test (a, b, c, y); + input a; + input signed [1:0] b; + input signed [2:0] c; + output y; + assign #(12.5, 14.5) y = ^(a ? b : c); +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog << EOT +module test (input [7:0] a, b, c, d, output [7:0] x, y, z); + assign #(20, 20, 25) x = a + b, y = b + c, z = c + d; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test (a, b, c, y); + localparam TIME_STEP = 0.011; + input signed [3:0] a; + input signed [1:0] b; + input signed [1:0] c; + output [5:0] y; + assign #(TIME_STEP, TIME_STEP, TIME_STEP) y = (a >> b) >>> c; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test; + localparam TIME_STEP = 0.7; + wire o, a, b; + and #(TIME_STEP, 2) and_gate (o, a, b); + wire #(0, TIME_STEP, TIME_STEP) x; + assign o = x; +endmodule +EOT + +design -reset +logger -expect warning "Yosys has only limited support for tri-state logic at the moment." 1 +read_verilog <<EOT +module test (input en, input a, input b, output c); + wire [15:0] add0_res = a + b; + assign #(3, 3) c = (en) ? a : 1'bz; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test (input en, d, t_rise, t_fall); + reg o; + always @* + if (en) + o = #(t_rise, t_fall, 50) ~d; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test #(parameter DELAY_RISE = 0, DELAY_FALL = 0, DELAY_Z = 0) + (input clock, input reset, input req_0, input req_1, output gnt_0, output gnt_1); + parameter SIZE = 3; + parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100; + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + reg gnt_0, gnt_1; + + always @ (state or req_0 or req_1) + begin : FSM_COMBO + next_state = 3'b000; + case (state) + IDLE : if (req_0 == 1'b1) begin + next_state = #(DELAY_RISE * 2) GNT0; + end else if (req_1 == 1'b1) begin + next_state = #(DELAY_RISE * 2.5, DELAY_FALL) GNT1; + end else begin + next_state = #(DELAY_RISE * 2.5, DELAY_FALL, DELAY_Z) IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + #(DELAY_RISE, DELAY_FALL) next_state = GNT0; + end else begin + #DELAY_RISE next_state = IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + #10 next_state = GNT1; + end else begin + #(10) next_state = IDLE; + end + default : next_state = IDLE; + endcase + end + + always @ (posedge clock) + begin : FSM_SEQ + if (reset == 1'b1) begin + #3 state <= IDLE; + end else begin + #(1, 3) state <= next_state; + end + end + + always @ (posedge clock) + begin : FSM_OUTPUT + if (reset == 1'b1) begin + gnt_0 <= #(DELAY_RISE, DELAY_FALL, DELAY_Z) 1'b0; + gnt_1 <= #1 1'b0; + end else begin + case (state) + IDLE : begin + gnt_0 <= #(DELAY_RISE, DELAY_FALL, DELAY_Z) 1'b0; + gnt_1 <= #1 1'b0; + end + GNT0 : begin + gnt_0 <= #(DELAY_RISE, DELAY_FALL) 1'b1; + gnt_1 <= #1 1'b0; + end + GNT1 : begin + gnt_0 <= #(DELAY_RISE) 1'b0; + gnt_1 <= #1 1'b1; + end + default : begin + gnt_0 <= 1'b0; + gnt_1 <= 1'b0; + end + endcase + end + end +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test; + reg q; + initial #(1,2) q = 1; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test #(parameter hyst = 16) + (input [0:1] inA, input rst, output reg out); + parameter real updatePeriod = 100.0; + initial out = 1'b0; + always #updatePeriod begin + if (rst) out <= 1'b0; + else if (inA[0] > inA[1]) out <= 1'b1; + else if (inA[0] < inA[1] - hyst) out <= 1'b0; + end +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test #(parameter hyst = 16) + (input [0:1] inA, input rst, output reg out); + parameter updatePeriod = (100:125:200); + initial out = 1'b0; + always #updatePeriod begin + if (rst) out <= 1'b0; + else if (inA[0] > inA[1]) out <= 1'b1; + else if (inA[0] < inA[1] - hyst) out <= 1'b0; + end +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test; + reg clk; + initial clk = 1'b0; + always #(100, 180, 230) clk = ~clk; +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test; + reg clk; + initial clk = 1'b0; + always clk = #(100, 180, 230) ~clk; + task t_test; + sig_036_A <= #(2, 4, 5.5) 0; + sig_036_B <= #(1.3, 3) 0; + sig_036_S <= #(2) 0; + #(100, 200, 300); + sig_036_A <= #(2 : 3 : 5) ~0; + sig_036_B <= #(4 : 6 : 6, 10) ~0; + sig_036_S <= #(1 : 2 : 3, 2 : 2 : 3, 10) ~0; + #100; + endtask +endmodule +EOT + +design -reset +logger -expect-no-warnings +read_verilog <<EOT +module test (clk, en, i, o); + input clk, en, i; + reg p; + output o; + always @ (posedge clk) + begin + if (en) begin + p <= #(5:15:25, 20, 30) i; + end else begin + #(5, 3:5:8, 10) p <= i; + end + end + assign #(10, 20, 15:20:30) o = p; +endmodule +EOT diff --git a/tests/verilog/func_arg_mismatch_1.ys b/tests/verilog/func_arg_mismatch_1.ys new file mode 100644 index 000000000..a0e82db0c --- /dev/null +++ b/tests/verilog/func_arg_mismatch_1.ys @@ -0,0 +1,12 @@ +logger -expect error "Incompatible re-declaration of wire" 1 +read_verilog -sv <<EOT +module top; + function automatic integer f; + input [0:0] inp; + integer inp; + f = inp; + endfunction + integer x, y; + initial x = f(y); +endmodule +EOT diff --git a/tests/verilog/func_arg_mismatch_2.ys b/tests/verilog/func_arg_mismatch_2.ys new file mode 100644 index 000000000..c2c29c1fb --- /dev/null +++ b/tests/verilog/func_arg_mismatch_2.ys @@ -0,0 +1,12 @@ +logger -expect error "Incompatible re-declaration of constant function wire" 1 +read_verilog -sv <<EOT +module top; + function automatic integer f; + input [0:0] inp; + integer inp; + f = inp; + endfunction + integer x; + initial x = f(0); +endmodule +EOT diff --git a/tests/verilog/func_arg_mismatch_3.ys b/tests/verilog/func_arg_mismatch_3.ys new file mode 100644 index 000000000..892824c09 --- /dev/null +++ b/tests/verilog/func_arg_mismatch_3.ys @@ -0,0 +1,12 @@ +logger -expect error "Incompatible re-declaration of wire" 1 +read_verilog -sv <<EOT +module top; + function automatic integer f; + input [1:0] inp; + integer inp; + f = inp; + endfunction + integer x, y; + initial x = f(y); +endmodule +EOT diff --git a/tests/verilog/func_arg_mismatch_4.ys b/tests/verilog/func_arg_mismatch_4.ys new file mode 100644 index 000000000..87ec1c299 --- /dev/null +++ b/tests/verilog/func_arg_mismatch_4.ys @@ -0,0 +1,12 @@ +logger -expect error "Incompatible re-declaration of constant function wire" 1 +read_verilog -sv <<EOT +module top; + function automatic integer f; + input [1:0] inp; + integer inp; + f = inp; + endfunction + integer x; + initial x = f(0); +endmodule +EOT diff --git a/tests/verilog/genblk_case.v b/tests/verilog/genblk_case.v new file mode 100644 index 000000000..081fb09d3 --- /dev/null +++ b/tests/verilog/genblk_case.v @@ -0,0 +1,26 @@ +module top; + parameter YES = 1; + generate + if (YES) wire y; + else wire n; + + if (!YES) wire n; + else wire y; + + case (YES) + 1: wire y; + 0: wire n; + endcase + + case (!YES) + 0: wire y; + 1: wire n; + endcase + + if (YES) wire y; + else wire n; + + if (!YES) wire n; + else wire y; + endgenerate +endmodule diff --git a/tests/verilog/genblk_case.ys b/tests/verilog/genblk_case.ys new file mode 100644 index 000000000..3c1bb51f9 --- /dev/null +++ b/tests/verilog/genblk_case.ys @@ -0,0 +1,15 @@ +read_verilog genblk_case.v + +select -assert-count 0 top/genblk1.n +select -assert-count 0 top/genblk2.n +select -assert-count 0 top/genblk3.n +select -assert-count 0 top/genblk4.n +select -assert-count 0 top/genblk5.n +select -assert-count 0 top/genblk6.n + +select -assert-count 1 top/genblk1.y +select -assert-count 1 top/genblk2.y +select -assert-count 1 top/genblk3.y +select -assert-count 1 top/genblk4.y +select -assert-count 1 top/genblk5.y +select -assert-count 1 top/genblk6.y diff --git a/tests/verilog/genblk_port_decl.ys b/tests/verilog/genblk_port_decl.ys new file mode 100644 index 000000000..589d3d2e1 --- /dev/null +++ b/tests/verilog/genblk_port_decl.ys @@ -0,0 +1,12 @@ +logger -expect error "Cannot declare module port `\\x' within a generate block\." 1 +read_verilog <<EOT +module top(x); + generate + if (1) begin : blk + output wire x; + assign x = 1; + end + endgenerate + output wire x; +endmodule +EOT diff --git a/tests/verilog/hidden_decl.ys b/tests/verilog/hidden_decl.ys new file mode 100644 index 000000000..aed7847dc --- /dev/null +++ b/tests/verilog/hidden_decl.ys @@ -0,0 +1,11 @@ +logger -expect error "Identifier `\\y' is implicitly declared and `default_nettype is set to none" 1 +read_verilog <<EOT +`default_nettype none +module top1; + wire x; + generate + if (1) wire y; + endgenerate + assign x = y; +endmodule +EOT diff --git a/tests/verilog/int_types.sv b/tests/verilog/int_types.sv new file mode 100644 index 000000000..8133f8218 --- /dev/null +++ b/tests/verilog/int_types.sv @@ -0,0 +1,47 @@ +`define TEST(typ, width, is_signed) \ + if (1) begin \ + typ x = -1; \ + localparam typ y = -1; \ + logic [127:0] a = x; \ + logic [127:0] b = y; \ + if ($bits(x) != width) \ + $error(`"typ doesn't have expected size width`"); \ + if ($bits(x) != $bits(y)) \ + $error(`"localparam typ doesn't match size of typ`"); \ + function automatic typ f; \ + input integer x; \ + f = x; \ + endfunction \ + logic [127:0] c = f(-1); \ + always @* begin \ + assert (x == y); \ + assert (a == b); \ + assert (a == c); \ + assert ((a == -1) == is_signed); \ + end \ + end + +`define TEST_INTEGER_ATOM(typ, width) \ + `TEST(typ, width, 1) \ + `TEST(typ signed, width, 1) \ + `TEST(typ unsigned, width, 0) + +`define TEST_INTEGER_VECTOR(typ) \ + `TEST(typ, 1, 0) \ + `TEST(typ signed, 1, 1) \ + `TEST(typ unsigned, 1, 0) \ + `TEST(typ [1:0], 2, 0) \ + `TEST(typ signed [1:0], 2, 1) \ + `TEST(typ unsigned [1:0], 2, 0) + +module top; + `TEST_INTEGER_ATOM(integer, 32) + `TEST_INTEGER_ATOM(int, 32) + `TEST_INTEGER_ATOM(shortint, 16) + `TEST_INTEGER_ATOM(longint, 64) + `TEST_INTEGER_ATOM(byte, 8) + + `TEST_INTEGER_VECTOR(reg) + `TEST_INTEGER_VECTOR(logic) + `TEST_INTEGER_VECTOR(bit) +endmodule diff --git a/tests/verilog/int_types.ys b/tests/verilog/int_types.ys new file mode 100644 index 000000000..c17c44b4c --- /dev/null +++ b/tests/verilog/int_types.ys @@ -0,0 +1,7 @@ +read_verilog -sv int_types.sv +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/macro_unapplied.ys b/tests/verilog/macro_unapplied.ys new file mode 100644 index 000000000..81eb10b8b --- /dev/null +++ b/tests/verilog/macro_unapplied.ys @@ -0,0 +1,17 @@ +logger -expect-no-warnings +read_verilog -sv <<EOT +`define MACRO(a = 1, b = 2) initial $display("MACRO(a = %d, b = %d)", a, b) +module top; + `MACRO(); +endmodule +EOT + +design -reset + +logger -expect error "Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'" 1 +read_verilog -sv <<EOT +`define MACRO(a = 1, b = 2) initial $display("MACRO(a = %d, b = %d)", a, b) +module top; + `MACRO; +endmodule +EOT diff --git a/tests/verilog/macro_unapplied_newline.ys b/tests/verilog/macro_unapplied_newline.ys new file mode 100644 index 000000000..a3f88d5b4 --- /dev/null +++ b/tests/verilog/macro_unapplied_newline.ys @@ -0,0 +1,5 @@ +logger -expect error "Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'" 1 +read_verilog -sv <<EOT +`define foo(a=1) (a) +`foo +EOT diff --git a/tests/verilog/param_int_types.sv b/tests/verilog/param_int_types.sv new file mode 100644 index 000000000..3228369b8 --- /dev/null +++ b/tests/verilog/param_int_types.sv @@ -0,0 +1,19 @@ +module gate(out); + parameter integer a = -1; + parameter int b = -2; + parameter shortint c = -3; + parameter longint d = -4; + parameter byte e = -5; + output wire [1023:0] out; + assign out = {a, b, c, d, e}; +endmodule + +module gold(out); + integer a = -1; + int b = -2; + shortint c = -3; + longint d = -4; + byte e = -5; + output wire [1023:0] out; + assign out = {a, b, c, d, e}; +endmodule diff --git a/tests/verilog/param_int_types.ys b/tests/verilog/param_int_types.ys new file mode 100644 index 000000000..7727801cf --- /dev/null +++ b/tests/verilog/param_int_types.ys @@ -0,0 +1,5 @@ +read_verilog -sv param_int_types.sv +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/verilog/unnamed_block.ys b/tests/verilog/unnamed_block.ys new file mode 100644 index 000000000..0f209a089 --- /dev/null +++ b/tests/verilog/unnamed_block.ys @@ -0,0 +1,28 @@ +read_verilog <<EOT +module top; + initial begin : blk + integer x; + end +endmodule +EOT + +delete + +read_verilog -sv <<EOT +module top; + initial begin + integer x; + end +endmodule +EOT + +delete + +logger -expect error "Local declaration in unnamed block is only supported in SystemVerilog mode!" 1 +read_verilog <<EOT +module top; + initial begin + integer x; + end +endmodule +EOT diff --git a/tests/verilog/unnamed_genblk.sv b/tests/verilog/unnamed_genblk.sv new file mode 100644 index 000000000..41828b1b0 --- /dev/null +++ b/tests/verilog/unnamed_genblk.sv @@ -0,0 +1,39 @@ +// This test is taken directly from Section 27.6 of IEEE 1800-2017 + +module top; + parameter genblk2 = 0; + genvar i; + + // The following generate block is implicitly named genblk1 + + if (genblk2) logic a; // top.genblk1.a + else logic b; // top.genblk1.b + + // The following generate block is implicitly named genblk02 + // as genblk2 is already a declared identifier + + if (genblk2) logic a; // top.genblk02.a + else logic b; // top.genblk02.b + + // The following generate block would have been named genblk3 + // but is explicitly named g1 + + for (i = 0; i < 1; i = i + 1) begin : g1 // block name + // The following generate block is implicitly named genblk1 + // as the first nested scope inside g1 + if (1) logic a; // top.g1[0].genblk1.a + end + + // The following generate block is implicitly named genblk4 since + // it belongs to the fourth generate construct in scope "top". + // The previous generate block would have been + // named genblk3 if it had not been explicitly named g1 + + for (i = 0; i < 1; i = i + 1) + // The following generate block is implicitly named genblk1 + // as the first nested generate block in genblk4 + if (1) logic a; // top.genblk4[0].genblk1.a + + // The following generate block is implicitly named genblk5 + if (1) logic a; // top.genblk5.a +endmodule diff --git a/tests/verilog/unnamed_genblk.ys b/tests/verilog/unnamed_genblk.ys new file mode 100644 index 000000000..2b9aa9d69 --- /dev/null +++ b/tests/verilog/unnamed_genblk.ys @@ -0,0 +1,8 @@ +read_verilog -sv unnamed_genblk.sv +select -assert-count 0 top/genblk1.a +select -assert-count 1 top/genblk02.b +select -assert-count 0 top/genblk1.a +select -assert-count 1 top/genblk02.b +select -assert-count 1 top/g1[0].genblk1.a +select -assert-count 1 top/genblk4[0].genblk1.a +select -assert-count 1 top/genblk5.a diff --git a/tests/verilog/wire_and_var.sv b/tests/verilog/wire_and_var.sv new file mode 100644 index 000000000..79c7c04c6 --- /dev/null +++ b/tests/verilog/wire_and_var.sv @@ -0,0 +1,33 @@ +`define TEST(kwd) \ + kwd kwd``_1; \ + kwd kwd``_2; \ + initial kwd``_1 = 1; \ + assign kwd``_2 = 1; + +`define TEST_VAR(kwd) \ + var kwd var_``kwd``_1; \ + var kwd var_``kwd``_2; \ + initial var_``kwd``_1 = 1; \ + assign var_``kwd``_2 = 1; + +`define TEST_WIRE(kwd) \ + wire kwd wire_``kwd``_1; \ + wire kwd wire_``kwd``_2; \ + initial wire_``kwd``_1 = 1; \ + assign wire_``kwd``_2 = 1; + +module top; + +`TEST(wire) // wire assigned in a block +`TEST(reg) // reg assigned in a continuous assignment +`TEST(logic) +`TEST(integer) + +`TEST_VAR(reg) // reg assigned in a continuous assignment +`TEST_VAR(logic) +`TEST_VAR(integer) + +`TEST_WIRE(logic) // wire assigned in a block +`TEST_WIRE(integer) // wire assigned in a block + +endmodule diff --git a/tests/verilog/wire_and_var.ys b/tests/verilog/wire_and_var.ys new file mode 100644 index 000000000..9359a9d55 --- /dev/null +++ b/tests/verilog/wire_and_var.ys @@ -0,0 +1,9 @@ +logger -expect warning "wire '\\wire_1' is assigned in a block" 1 +logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1 + +logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1 + +logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1 +logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1 + +read_verilog -sv wire_and_var.sv |