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-rw-r--r--tests/sva/runtest.sh7
-rw-r--r--tests/techmap/.gitignore1
-rw-r--r--tests/techmap/mem_simple_4x1_runtest.sh16
3 files changed, 5 insertions, 19 deletions
diff --git a/tests/sva/runtest.sh b/tests/sva/runtest.sh
index 1b65ca9c9..8ed7f8cbc 100644
--- a/tests/sva/runtest.sh
+++ b/tests/sva/runtest.sh
@@ -22,18 +22,17 @@ generate_sby() {
if [ -f $prefix.sv ]; then
if [ "$1" = "fail" ]; then
- echo "verific -sv ${prefix}_fail.sv"
+ echo "read -sv ${prefix}_fail.sv"
else
- echo "verific -sv $prefix.sv"
+ echo "read -sv $prefix.sv"
fi
fi
if [ -f $prefix.vhd ]; then
- echo "verific -vhdl $prefix.vhd"
+ echo "read -vhdl $prefix.vhd"
fi
cat <<- EOT
- verific -import -extnets -all top
prep -top top
chformal -early -assume
diff --git a/tests/techmap/.gitignore b/tests/techmap/.gitignore
index cfed22fc5..56c9ba8f9 100644
--- a/tests/techmap/.gitignore
+++ b/tests/techmap/.gitignore
@@ -1,2 +1,3 @@
*.log
+*.out
/*.mk
diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh
index b486de5c7..5b5838b9d 100644
--- a/tests/techmap/mem_simple_4x1_runtest.sh
+++ b/tests/techmap/mem_simple_4x1_runtest.sh
@@ -1,17 +1,3 @@
#!/bin/bash
-set -e
-
-../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'read_verilog mem_simple_4x1_uut.v; proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat'
-
-iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v
-iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v
-
-./mem_simple_4x1_gold_tb > mem_simple_4x1_gold_tb.out
-./mem_simple_4x1_gate_tb > mem_simple_4x1_gate_tb.out
-
-diff -u mem_simple_4x1_gold_tb.out mem_simple_4x1_gate_tb.out
-rm -f mem_simple_4x1_synth.v mem_simple_4x1_tb.vcd
-rm -f mem_simple_4x1_{gold,gate}_tb{,.out}
-: OK
-
+exec ../tools/autotest.sh -G -j $@ -p 'proc; opt; memory -nomap; techmap -map ../mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v